Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.

Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.

Abstract: The present invention provides a search window delay tracking procedure for use in a multipath search processor of a CDMA radio receiver. A channel impulse response is estimated for a received signal containing plural paths, each path having a corresponding path delay. A search window defines a delay profile that contains the plural paths of the received signal. A mean or average delay is calculated for the estimated channel impulse response (CIR), and an error is determined between the mean CIR delay and a desired or target delay position of the Cir. search window. An adjustment is made to reduce that error to align the targeted position of the search window and the mean CIR delay. A Doppler frequency is estimated for each path. The adjustment is made taking into account a Doppler effect caused by relative movement between the transmitter and receiver.

Abstract: The present invention provides a search window delay tracking procedure for use in a multipath search processor of a CDMA radio receiver. A channel impulse response is estimated for a received signal containing plural paths, each path having a corresponding path delay. A search window defines a delay profile that contains the plural paths of the received signal. A mean or average delay is calculated for the estimated channel impulse response (CIR), and an error is determined between the mean CIR delay and a desired or target delay position of the Cir. search window. An adjustment is made to reduce that error to align the targeted position of the search window and the mean CIR delay. A Doppler frequency is estimated for each path. The adjustment is made taking into account a Doppler effect caused by relative movement between the transmitter and receiver.

Abstract: A method of rate detection at a receiving end of a code division multiple access (CDMA) system, in which system the effective data rate is variably selected at the transmitting end from an applicable rate set including a full rate and lower rates, each lower rate being the full rate divided by a different integer, and encoded symbols are repeated for the lower rates to maintain a constant apparent symbol transmission rate, includes the formation of scaled correlations between data entering a Viterbi decoder, after any required de-repetition, and re-encoded data at each of the possible data rates in the applicable rate set. Rate decision logic sequentially considers the full and lower candidate data rates in descending order, choosing the considered candidate data rate to be the actual data rate if certain conditions are met.

Abstract: A method of rate detection at a receiving end of a code division multiple access (CDMA) system, in which system the effective data rate is variably selected at the transmitting end from an applicable rate set including a full rate and lower rates, each lower rate being the full rate divided by a different integer, and encoded symbols are repeated for the lower rates to maintain a constant apparent bit or symbol transmission rate. The data rate is first determined by a coarse decision method employing symbol repetition characteristics before any Viterbi decoding of the data, the data is de-punctured and de-repeated where required, and first Viterbi decoded at the first determined data rate, and data available from or after the first Viterbi decoding is evaluated to determine whether to select the data rate as equal to the first determined data rate.