Abstract: A dielectrically isolated semiconductor device which is substantially planar can be manufactured. The structure is useable for integrated circuits wherein a significant savings in surface area can be obtained over prior techniques. The structure is particularly useful for bipolar integrated circuits wherein a semiconductor substrate with an epitaxial layer thereon contains a buried region partially in the substrate and in the epitaxial layer. The emitter and base regions are located in the epitaxial layer above the buried region. The dielectrically isolating region surrounds the emitter and base region at the surface and extends to a depth wherein it intersects with the buried region to fully isolate the device. The buried region is connected as the collector element of the transistor.

Abstract: A method for selectively depositing a plurality of metal layers on a substrate. The method includes the steps of depositing at least one layer of blanket metal on a surface of a substrate, building a lift-off stencil over the blanket metal, depositing at least one layer of redundant metal over the lift-off stencil, depositing a first etch-resistant barrier over the redundant metal, removing the lift-off stencil and the overlying layers of redundant metal and the etch-resistant barrier, depositing a second etch-resistant barrier over the blanket metal and the first etch-resistant barrier, and then reactive ion etching (RIE) the second etch-resistant barrier so as to expose the blanket metal and at least partially remove the second etch-resistant barrier from the first etch-resistant barrier. A final step of the method includes etching the blanket metal. Also disclosed is a metallurgical structure for a packaging substrate. The metallurgical structure includes layers of blanket metal and redundant metal.

Abstract: A method of forming on a substrate a pattern of structures having a thickness on the order of one micron or less. A first insulating layer is formed on a major surface of a substrate, for example, a silicon body. A polycrystalline silicon layer is formed thereover and openings are formed therein by reactive ion etching to provide substantially horizontal surfaces and substantially vertical sidewalls. The vertical sidewalls of the openings are formed at the desired locations of the narrow dimensioned structures. A second, conformal insulating layer is then formed followed by a reactive ion etching step which substantially removes the horizontal portions of the second insulating layer. The remaining polycrystalline silicon layer is removed to leave a pattern of self-supporting narrow dimensioned dielectric regions on the major surface of the substrate. The narrow dimensioned dielectric regions can be used as a mask to form narrow structures in the substrate.

Abstract: A self-aligned metal integrated circuit structure is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces.

Abstract: A PNP semiconductor device and a manufacturing method therefore. In the method, a window is formed on the surface of a semiconductor substrate having an N-type base region formed therein. A polycrystalline layer is formed on the base region in the window. The polycrystalline silicon layer is ion implanted under specific predetermined conditions with a P-type doping ion. The P-type doping ion is diffused by an annealing treatment under predetermined conditions into the base region to form a shallow emitter region.

Abstract: A self-aligned metal field effect transistor is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar.

Abstract: Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conductivity type. Then, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate.In a preferred embodiment the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base.

Abstract: A transistor structure is provided with an emitter which is formed from non-monocrystalline silicon which is caused to be converted to monocrystalline silicon during the manufacture of the transistor. In the process of manufacturing the present semiconductor structure, a subcollector is formed in a semiconductor substrate. The subcollector dopant out diffuses into a subsequently deposited epitaxial layer. A base region is formed in the epitaxial layer of a conductivity type opposite that of the conductivity type of the subcollector. This results in a PN junction between the base region and the out diffused subcollector impurities forming the collector of the transistor.A layer of non-monocrystalline silicon is deposited on the epitaxial layer. At least a portion of the non-monocrystalline silicon forms a precursor for an emitter region which is contiguous to but vertically displaced from the surface of the base region.

Abstract: A self-aligned metal process is described which achieves self-aligned metal silicon contacts and micron-to-submicron contact-to-contact and metal-to-metal spacing by use of the pattern of dielectric material having a thickness in the order of a micron or less. The pattern of recessed oxide isolation to device area is also self-aligned by this process. The process results in substantially planar integrated circuit structure. The process is applicable to either a bipolar integrated circuit either bipolar or MOS field effect transistor integrated circuits.

Abstract: A self-aligned metal process is decribed which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces.

Abstract: A dielectrically isolated semiconductor device can be manufactured. The structure is useable for integrated circuits, including field effect and/or bipolar transistors, wherein a significant savings in surface area and reduction in capacitances can be obtained over prior techniques. The method involves forming a layer of dielectric material upon a semiconductor body, having a diffused region where a bipolar device is to be formed, and then forming an opening in the layer to expose a part of the surface of the diffused region of the semiconductor body. An epitaxial layer of silicon is deposited on top. Single crystal silicon will grow over the exposed silicon area and if a diffused region is present in the substrate a pedestal will outdiffuse through the same area from the buried diffused region. Polycrystalline silicon will grow on top of the dielectric material. The pedestal is formed in a single crystal epitaxial layer of another impurity type.

Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron or less. The structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the layer by reactive ion etching which results in the structure having horizontal surfaces and vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal surfaces and vertical surfaces.

Abstract: Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region.

Abstract: A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I.sup.2 L) technology. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. The first insulating layer is removed in areas designated to contain integrated injection logic devices. A layer of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit.

Abstract: Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets.

Abstract: In the fabrication of semiconductor integrated circuits, a method is provided for forming a self-supporting silicon mask and a further method is provided for utiliziing such a self-supporting separable silicon mask to perform various masking steps in the integrated circuit fabrication.The mask is formed by forming, at a surface of a planar silicon substrate, a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath the layer, applying to selected portions of the other surface of the substrate an etchant which preferentially etches silicon having lower concentrations of conductivity-determining impurities to thus etch out preferentially selected portions of the substrate to form at least one recess extending through the substrate to said silicon layer, and then etching from the surface of said silicon layer opposite the substrate recess to form patterns of openings extending through the silicon layer to said substrate recess.

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer.In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact.

Abstract: A process for fabricating devices having overlapping heavily doped impurity regions of opposite conductivity wherein the formation of crystallographic faults emanating from the overlapping regions is eliminated. It has been discovered that crystallographic faults can be avoided by limiting the total N and P impurity concentrations in the overlapped regions. The process includes forming in the semiconductor substrate a first arsenic doped region having a maximum impurity concentration in the range of 5.times.10.sup.20 to 3.times.10.sup.21 atoms/cc, and forming in the silicon substrate a second adjacent boron doped region in partial overlapping relation to the first region having a maximum impurity concentration in the range of 5.times.10.sup.19 to 3.times.10.sup.20 atoms/cc.

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer.In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact.

Abstract: In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a silicon substrate comprising initially introducing conductivity-determining impurities into the substrate to form at least one region of one-type conductivity at the surface of said substrate. Then, a mask comprising a composite of a bottom layer of silicon dioxide and a top layer of silicon nitride is formed over at least a portion of the surface of said introduced regions. The substrate is then subsequently thermally oxidized to an extent sufficient to form regions of recessed silicon dioxide abutting and thus laterally defining said region of one-type conductivity. In this manner, it is ensured that the recessed silicon dioxide will abut introduced region irrespective of the extent of the "bird's beak" normally associated with thermal oxidation utilizing silicon dioxide-silicon nitride masking.