Patents by Inventor Ingrid Emese Magdo

Ingrid Emese Magdo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure with annular collector/subcollector region
    Patent number: 4079408
    Abstract: Disclosed is a semiconductor structure with an annular collector/subcollector region. The base area with the emitter, is positioned over the collector/subcollector region only, resulting in a smaller base to collector capacitance. Packing density is improved and circuit design flexibility is provided by the ability to change the emitter size without changing the size of the overall structure.
    Type: Grant
    Filed: December 31, 1975
    Date of Patent: March 14, 1978
    Assignee: International Business Machines Corporation
    Inventors: Theodore William Kwap, Ingrid Emese Magdo
  • High performance integrated bipolar and complementary field effect transistors
    Patent number: 4016596
    Abstract: A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BV.sub.ceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.
    Type: Grant
    Filed: January 26, 1976
    Date of Patent: April 5, 1977
    Assignee: International Business Machines Corporation
    Inventors: Ingrid Emese Magdo, Steven Magdo
  • Fabricating high performance integrated bipolar and complementary field effect transistors
    Patent number: 3955269
    Abstract: A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BV.sub.ceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.
    Type: Grant
    Filed: June 19, 1975
    Date of Patent: May 11, 1976
    Assignee: International Business Machines Corporation
    Inventors: Ingrid Emese Magdo, Steven Magdo