Abstract: A random number generator includes an entropy source comprising a first digital device arranged to apply to an input signal a first delay value to obtain a first signal and a second digital device arranged to apply to the input signal a second delay value different from the first delay value to obtain a second signal; a sampling unit configured to sample one of the first and second signals using the other signal as reference clock, thereby obtaining a sampled signal; measurement means to perform measurements of the sampled signal's delay difference with respect to the reference clock; a controller circuit arranged to monitor the measured delay difference of the sampled signal and to check the values of the measured delay difference and, once a given condition related to the values is met, to output a configuration signal.

Abstract: Wave Dynamic Differential Logic (WDDL) is provided, wherein a differential logic stage is pre-charged or pre-discharged by a previous logic stage, such as, for example, a previous SDDL stage, a WDDL stage, etc. In one embodiment, a Divided Wave Dynamic Differential Logic (DWDDL) is provided wherein a WDDL circuit is conveniently implemented as dual logic trees.

Abstract: Methods for differential pair conductor routing in a logic circuit. One embodiment includes a method for differential pair conductor routing in a logic circuit, by routing conductors of a first line width to obtain a first routing for a first logic library, wherein vertical and horizontal paths are separated such that vertical and horizontal conductors do not short, wherein connections between the vertical and horizontal paths are provided by vias, separating conductor paths in the first routing into differential paths by splitting the conductors of a first line width into spaced parallel conductors of a second line width, where the second line width is smaller than the first line width, separating the vias into pairs of vias, and replacing the first logic library with a differential logic library.

Abstract: DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA-blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed.

Abstract: DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA -blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed.

Abstract: DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA-blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed.

Abstract: An advanced encryption system (AES) architecture includes a maximum parallel encryption module which implements one round of the AES algorithm in one clock cycle, and a maximum parallel key scheduling module which generates sub-keys in one clock cycle in parallel with the encryption module, thereby permitting feedback modes of operation to be used without adversely affecting AES throughput. A controller controls the operation of the encryption and key scheduling modules such that one round is completed per clock cycle. The controller is preferably part of a hierarchical distributed control scheme comprising communicating finite state machines (FSMs). The architecture also preferably includes asynchronous input and output buffers.

Abstract: An advanced encryption system (AES) architecture includes a maximum parallel encryption module which implements one round of the AES algorithm in one clock cycle, and a maximum parallel key scheduling module which generates sub-keys in one clock cycle in parallel with the encryption module, thereby permitting feedback modes of operation to be used without adversely affecting AES throughput. A controller controls the operation of the encryption and key scheduling modules such that one round is completed per clock cycle. The controller is preferably part of a hierarchical distributed control scheme comprising communicating finite state machines (FSMs). The architecture also preferably includes asynchronous input and output buffers.

Abstract: A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the in-put value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase.

Abstract: A secure embedded system that uses cryptographic and biometric signal processing acceleration is described. In one embodiment, the secure embedded system is configured as a wireless pay-point protocol for brick-and-mortar and e-commerce applications in which biometric information is localized and does not require transmission of biometric data for authentication. In one embodiment, a key-generation function uses a dynamic key generator and static biometric components. In one embodiment, an embedded system design methodology provides hardware and software acceleration transparency.

Abstract: A fully alternating current (AC) coupled multi-point, multi-drop or point-to-point bus interconnect uses a low power synchronous pulsed signaling scheme for board-level chip-to-chip communication. A single-ended or differential pulsed signaling transceiver generates a diamond data eye with a small time constant in the pulsed signal. The transceiver includes a high-pass filter or a differentiator circuit network that generates triangle pulses that make the diamond data eye.

Abstract: An advanced encryption system (AES) architecture includes a maximum parallel encryption module which implements one round of the AES algorithm in one clock cycle, and a maximum parallel key scheduling module which generates sub-keys in one clock cycle in parallel with the encryption module, thereby permitting feedback modes of operation to be used without adversely affecting AES throughput. A controller controls the operation of the encryption and key scheduling modules such that one round is completed per clock cycle. The controller is preferably part of a hierarchical distributed control scheme comprising communicating finite state machines (FSMs). The architecture also preferably includes asynchronous input and output buffers.

Abstract: A multiplier architecture in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure in order to achieve a small floor plan when reduced to silicon. A Hekstra-type multiplier is modified by replacing full adders circuits with compressor circuits in a manner that preserves the balance of the signal propagation delays. The result is an architecture having a regular layout that greatly facilitates its implementation in silicon.

Abstract: A digital signal processing system for executing instructions and processing data, including a program memory which stores the instructions and a first portion of the data, a data memory which stores a second portion of the data, and a program control unit connected to the program memory for receiving a sequence of the instructions and generating control signals for executing the instructions, wherein the program control unit is programmed to fetch at least one data value from the program memory in response to at least one of the instructions. Preferably, the system also includes a memory management unit connected to the program control unit and the data memory for generating address signals in response to at least one of the control signals for use in reading data values from the data memory.

Abstract: A digital signal processing system for executing instructions and processing data, including a program memory which stores encoded instructions, where the program memory consumes less power when a bit having a first logical level is read therefrom than when a bit having a second logical level is read therefrom, and where the most commonly read encoded instructions comprise more (and preferably many more) bits having the first logical level than bits having the second logical level. Preferably, the program memory is implemented as a read-only memory (ROM). Other aspects of the invention are a method for generating such encoded instructions and storing the encoded instructions in a ROM, a ROM which stores such encoded instructions, a digital signal processing system having a read-only program memory storing such encoded instructions, and methods for operating such a processing system.

Abstract: A digital signal processing system and method for executing instructions with decode, read, execute, and write pipeline cycles. In the decode cycle, control signals are generated which determine addresses which in turn determine memory locations from which data are to be read and to which processed data are to be written. The system includes a program control unit for processing a sequence of instructions and controlling system operation, a memory, a data processing unit, and a dedicated bus for writing processed data from the data processing unit to the memory. By using a dedicated write bus, the system avoids bus contention in a five stage pipeline operation involving fetch, decode, read, execute, and write operations. A post shift unit connected along the write bus shifts data values that have been output from the data processing unit before they are written to the memory.

Abstract: A digital signal processing system for executing instructions, including a program memory which stores the instructions and a program control unit for receiving and processing a sequence of the instructions to generate control signals for controlling operation of the system, and a loop circuit for use in such a program control unit. The loop circuit controls execution of a loop (preferably a nested loop) of a sequence of the instructions. Preferably, the loop circuit includes loop registers for storing loop start and end addresses and loop count values, and logic circuitry for implementing loops (including nested loops) in response to the addresses and count values in the loop registers. The loop circuit is initialized by loading appropriate addresses and values into the loop registers.