Abstract: A semiconductor package includes a package substrate, a semiconductor chip on an upper surface of the package substrate, the semiconductor chip having a first surface facing the package substrate and a second surface opposite to the first surface, the semiconductor chip having a first thermal expansion coefficient, a stress control layer on the second surface of the semiconductor chip, the stress control layer having a second thermal expansion coefficient greater than the first thermal expansion coefficient so as to have a residual stress in a compressive direction, and a sealing member on the upper surface of the package substrate and covering the semiconductor chip and the stress control layer.

Abstract: Provided is a semiconductor package, the semiconductor package including: a package substrate having an upper surface on which a plurality of bonding pads are arranged; a semiconductor chip disposed on the package substrate, and having an upper surface on which a plurality of chip pads are arranged; an adhesive layer extending onto the upper surface of the package substrate between the semiconductor chip and the package substrate; a dam structure disposed around the adhesive layer, and surrounding a side surface of the adhesive layer; and external connection bumps disposed below the package substrate, and electrically connected to the plurality of bonding pads, wherein the external connection bumps are located below a region covered by the adhesive layer of the package substrate, and an area of the adhesive layer is greater than an area of a region in which the external bumps are disposed.

Abstract: A semiconductor package includes a package substrate a first semiconductor chip disposed on an upper surface of the package substrate, a dam structure disposed within the pad free region on the first surface of the first semiconductor chip, a first spacer chip attached to the upper surface of the package substrate, a plurality of second semiconductor chips stacked on the first spacer chip and the first semiconductor chip using adhesive films, first bonding wires electrically connecting each of the first chip pads of the first semiconductor chip to each of first substrate pads of the package substrate, respectively, and a molding covering the first spacer chip, the first semiconductor chip, and the plurality of second semiconductor chips. The first semiconductor chip includes a pad region on which the first chip pads are disposed and a pad free region. The spacer chip is spaced apart from the first semiconductor chip along a first direction.

Abstract: The present disclosure relates to a semiconductor package. An embodiment of the present disclosure provides a semiconductor package including: a package substrate; a semiconductor chip positioned on a first surface of the package substrate; a pad positioned on a second surface of the package substrate; a solder resist layer including an opening positioned on the second surface of the package substrate and the pad, the solder resist layer vertically overlapping at least a portion of the pad, the solder resist layer including a dummy opening spaced apart from the opening; and a filling layer positioned within the dummy opening, wherein the dummy opening is positioned farther than the opening from a center of the package substrate in a plan view.

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip on an upper surface of the package substrate, a spacer chip on the upper surface of the package substrate and spaced apart from the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the spacer chip by a plurality of adhesive films, respectively, and a molding member on the spacer chip, the first semiconductor chip, and the plurality of second semiconductor chips. When viewed in a plan view, the spacer chip has an overlapping region overlapping with a lowermost second semiconductor chip of the plurality of second semiconductor chips. The lowermost second semiconductor chip is attached to the spacer chip by a first adhesive film. A portion of the first adhesive film attached to the spacer chip is within a recess that is in an upper surface of the overlapping region of the spacer chip.

Abstract: Provided is an electronic device including a printed circuit board (PCB), a multilayer ceramic capacitor mounted on the PCB, wherein the multilayer ceramic capacitor includes a ceramic body and a plurality of internal electrodes inside the ceramic body, and an insulating layer between the PCB and the multilayer ceramic capacitor, wherein the insulating layer is in contact with the PCB and the multilayer ceramic capacitor.

Abstract: A semiconductor package includes: a package substrate that includes a substrate pad; a semiconductor chip that is disposed on the package substrate, the semiconductor chip including a chip pad; a bonding wire that connects the substrate pad to the chip pad; an adhesive member between the package substrate and the semiconductor chip; and a dam that extends along a side surface of the adhesive member and surrounds at least some of side surfaces of the adhesive member. A height of the dam is greater than or equal to a height of the adhesive member.

Abstract: A semiconductor package includes a package substrate including an insulating layer, an interconnection layer in the insulating layer, and interconnection pads on the insulating layer and electrically connected to the interconnection layer, first and second semiconductor chips on the package substrate and spaced apart from each other, first connection wires each extending from a first side of the first semiconductor chip to a second side of the second semiconductor chip and spaced apart from each other, an adhesive layer on the first and second semiconductor chips and covering at least a portion of each of the first connection wires, an upper semiconductor chip on the adhesive layer, second connection wires connecting the first and second semiconductor chips and the upper semiconductor chip to the interconnection layer of the package substrate, and an encapsulant on the package substrate and filling a space between the first and second semiconductor chips.

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.