Abstract: A semiconductor memory may include: a first variable resistance element including a first terminal and a second terminal; a second variable resistance element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element; a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element; a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element; and a third conductive line is electrically connected to the connection layer.

Abstract: An embodiment of the disclosure provides a display device including a substrate including a display area, and a peripheral area disposed on a side of the display area, a first alignment electrode, a second alignment electrode, and a third alignment electrode that overlap the display area, are spaced apart from each other in a first direction, and extend in a second direction intersecting the first direction, light emitting elements disposed between the first alignment electrode and the second alignment electrode, and between the second alignment electrode and the third alignment electrode, and a data line overlapping the second alignment electrode in a plan view and extending in the second direction. A length of a first width of the data line in the first direction is less than or equal to a length of a second width of the second alignment electrode in the first direction.

Abstract: A method of reading data from a self-selecting memory includes generating a read pulse that has a polarity opposite to that of a write pulse. The write pulse writes data into a target memory cell in the self-selecting memory. The read pulse is applied to the target memory cell. The read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse. A slope of the second edge of the read pulse is adjusted such that an undershoot or overshoot on the second edge of the read pulse increases.

Abstract: A virtual gear shift control apparatus for an electric vehicle is disclosed. The apparatus includes a driving information detector that detect information indicating a vehicle driving state. The apparatus also includes a controller that generates a motor torque command for satisfying a driver's demand torque based on the vehicle driving information including the information detected by the driving information detector. The controller determines whether the vehicle driving state of the electric vehicle corresponds to a predetermined power-off condition, determines, in response to a determination that the vehicle driving state corresponds to the predetermined power-off condition, a coasting torque corresponding to a current virtual gear stage and a current virtual engine speed. The controller also generates a motor torque command using the determined coasting torque as a command value.

Abstract: In a system and method for controlling the electric vehicle, the method for controlling the electric vehicle may be performed by a controller. The method may include obtaining virtual shift information based on drive information of the electric vehicle, detecting a power-on upshift based on the virtual shift information, in response to the detecting of the power-on upshift, determining whether a set condition for push-feel control is satisfied, and based on whether the set condition is satisfied, performing a torque control for a motor of the electric vehicle in either a normal control mode or a push-feel control mode.

Abstract: A launch control system and method for an electric vehicle, which are capable of satisfying a driver's demand for a high-performance vehicle by realizing the high performance of the electric vehicle. The system and method maximize acceleration at an initial stage of launching the electric vehicle from a standstill, thereby shortening the time to reach the maximum acceleration when launching the electric vehicle from the standstill.

Abstract: A method of guiding a shiftable gear stage of a vehicle provides information about a shiftable gear stage by a driver in a manual shift mode of a virtual gear shift system of the vehicle. The method includes: determining, by a control unit, whether a virtual gear shift system of an electric vehicle enters a manual shift mode; when the virtual gear shift system enters the manual shift mode; determining a shiftable gear stage by a driver on the basis of a current vehicle speed; and outputting and displaying the determined shiftable gear stage on a display device inside the electric vehicle.

Abstract: A method of guiding vehicle shift timing which may provide information related to the shift timing to a driver includes determining, by a controller, a virtual engine speed of an electric vehicle, determining, by the controller, a predicted speed limit arrival time taken for the determined virtual engine speed to reach a predetermined speed limit, controlling, by the controller, operation of a shift indicator configured to guide manual shift timing based on the determined virtual engine speed and predicted speed limit arrival time, and operating, by the controller, the shift indicator to provide shift timing information to the driver.

Abstract: A method for controlling a virtual engine sound of an electric vehicle, may include steps of, which are performed by a controller, collecting a driving state including the vehicle speed of the electric vehicle and the opening amount of an accelerator pedal, determining a virtual gear position based on the vehicle speed of the electric vehicle and the opening amount of the accelerator pedal, obtaining the virtual engine speed of the electric vehicle based on the vehicle speed and the virtual gear position, and outputting a virtual engine sound corresponding to the virtual engine speed.

Abstract: A semiconductor device may include a color filter array, an optical synapse array including a plurality of light passage paths transferring light incident through the color filter array with independently controlled transmissivities, and an optical-to-digital conversion circuit converting the transferred light through the plurality of light passage paths into digital data.

Abstract: A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

Abstract: The present specification provides: a method for generating a virtual organoid having various shapes and features; and a virtual organoid imaging method capable of obtaining the same effect as image data obtained from an actual organoid. The virtual organoid generation method according to the present specification may generate data relating to an organoid structure in a virtual space so as to apply the feature of an actual organoid. The imaging method using the virtual organoid according to the present specification enables generation of image data which can obtain the same effect as capturing an image of an actual organoid.

Abstract: A method for fabricating a semiconductor device includes forming a stack body including a recess target layer over a lower structure; forming sacrificial isolation openings in the stack body; forming sacrificial isolation layers including blocking layers in the sacrificial isolation openings; forming sacrificial vertical openings in the stack body between the sacrificial isolation layers; forming a preliminary horizontal layer by recessing the recess target layer of the stack body through the sacrificial vertical openings; forming a first dielectric layer that covers the preliminary horizontal layer; forming a second dielectric layer over the first dielectric layer; forming cell isolation openings by removing the sacrificial isolation layers; and trimming the first dielectric layer through the cell isolation openings.

Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Abstract: A method for isolating a lithium precursor according to an embodiment of the present disclosure includes preparing a preliminary precursor mixture including a preliminary lithium precursor and a preliminary transition metal precursor, mixing the preliminary precursor mixture and a precipitation liquid in a reactor to form a precursor mixture, and injecting a non-reactive gas into the precursor mixture. Accordingly, the lithium precursor can be isolated with high yield and high efficiency.

Abstract: Subsurface property estimation methods are disclosed. In an embodiment, a subsurface property estimation method may include creating, by a computer device, a training data set by preprocessing well-log data and first seismic data, the computer device including at least one processor for executing computer-readable instructions included in a data storage device; creating, by the computer device, an estimation model by using the training data set, the estimation model including: an encoder model configured to create a latent space that reflects features of strata based on input data; a decoder model configured to generate a first factor corresponding to a subsurface property based on the latent space; and a regression model configured to estimate a second factor corresponding to the subsurface property based on the latent space; and estimating the second factor corresponding to the subsurface property by inputting second seismic data to the estimation model.

Abstract: The present invention relates to a vagus nerve stimulation device for animals, the device comprising an electrode that contacts the animal's skin to transmit electrical stimuli and a power source for generating electrical stimuli transmitted to the electrode. The present invention has an excellent effect of stabilizing the psychological state of an animal by stimulating the vagus nerve from the outside of the animal. For companion animals, the present invention has the effect of eliminating aggression, relieving and stress, reducing separation anxiety. In the case of livestock animals, there are the effects of improving meat quality and increasing milk production by reducing breeding stress even without the aid of drugs or the like. For leisure animals or sports animals, the excellent effects of imparting psychological stability to reduce the risk of accidents due to psychological stability, improving recovery from fatigue, and improving exercise ability can be brought about.

Abstract: A nonvolatile memory device is provided to include a plurality of memory cells operable to store data, each memory cell structured to include a resistance change layer exhibiting different resistance states with different resistance values for representing data, a write circuit suitable for generating a write pulse in a write mode to write data in a memory cell of the plurality of memory cells, and a read circuit suitable for generating a read pulse in a read mode to read data from a memory cell of the plurality of memory cells, wherein the memory cells are each structured to be operable in writing or reading data when a range of a voltage level change of the read pulse corresponding to a pulse width change of the read pulse is within a range of a voltage level change of the write pulse corresponding to a pulse width change of the write pulse.