Abstract: A display device including a pixel comprises an EVDD driving unit outputting an AC driving voltage swinging between a high potential voltage and a low potential voltage according to voltages of a first control node and a second control node, and a plurality of sub-pixels connected to a data line and a gate line to receive the AC driving voltage by sharing an output node of the EVDD driving unit. Each of the sub-pixels may include a light emitting element, a driving element for supplying a current to the light emitting element according to a gate-source voltage, a switch element turned-on according to a scan signal to connect the data line to the gate of the driving element, and a capacitor connected between a gate and a source of the driving element.

Abstract: Discussed is a display device including a gate electrode, a gate insulating film disposed on the gate electrode, a semiconductor layer disposed on the gate insulating film, an insulating layer disposed on the semiconductor layer, a first electrode disposed on the insulating layer, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer.

Abstract: The present disclosure relates to an OLED display panel for minimizing the size of a bezel and includes: an active area including data lines, scan lines intersecting the data lines, and sub-pixels arranged at each intersection; and a stage of a GIP driving circuit distributed and arranged in a plurality of unit pixel regions driven by m (m being a natural number) scan lines in the active area, to supply scan pulses to the corresponding scan lines, wherein the active area further includes m GIP internal connection lines parts respectively adjacent to the m scan lines, and a plurality of internal connection lines for connecting elements constituting each stage is distributed and arranged in the m GIP internal connection line parts.

Abstract: The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines.

Abstract: A display device including a pixel comprises an EVDD driving unit outputting an AC driving voltage swinging between a high potential voltage and a low potential voltage according to voltages of a first control node and a second control node, and a plurality of sub-pixels connected to a data line and a gate line to receive the AC driving voltage by sharing an output node of the EVDD driving unit. Each of the sub-pixels may include a light emitting element, a driving element for supplying a current to the light emitting element according to a gate-source voltage, a switch element turned-on according to a scan signal to connect the data line to the gate of the driving element, and a capacitor connected between a gate and a source of the driving element.

Abstract: A display panel and an OLED display device using the same are disclosed. The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines.

Abstract: A display panel and an OLED display device using the same are disclosed. The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines.

Abstract: The present disclosure relates to an OLED display panel and an OLED display device in which a GIP driving circuit is arranged in an active area in order to minimize a bezel size and a GIP signal is applied to the GIP driving circuit arranged in the active area using a single-sided COF, and the OLED display panel includes: an active area including data lines, scan lines intersecting the data lines, and sub-pixels arranged at each intersection; stages of a GIP driving circuit distributed and arranged in a plurality of unit pixel regions corresponding to the scan lines in the active area to supply scan pulses to the scan lines; and a non-active area including a pad part, a link part and a LOG part, wherein the pad part includes a gate pad part for supplying various control signals to the stages of the GIP driving circuit, and a data pad part for supplying a data voltage to each data line, and wherein the non-active area includes a plurality of signal lines extended from the gate pad part via the link part to the

Abstract: Disclosed herein are a gate driver including at least two output buffers to drive at least two gate lines and capable of reducing an output deviation of each output buffer, and a flat panel display device including the same. The gate driver includes a plurality of gate-in-panels (GIPs) for sequentially supplying scan signals to a plurality of gate lines. Each GIP includes one carry signal output unit and at least two scan signal output units to drive at least two gate lines, and the carry signal output unit includes a pull-up transistor controlled by a voltage of a first node, a pull-down transistor controlled by a voltage of a second node, and a boosting capacitor formed between gate and source electrodes of the pull-up transistor.

Abstract: Disclosed herein is an organic light emitting diode (OLED) display device including an OLED display panel including a non-active area and an active area, having a plurality of gate lines and a plurality of data lines disposed in the active area, and having a plurality of subpixels arranged at intersections between the gate lines and the data lines in a matrix, a gate driver disposed in the non-active area of the OLED display panel to supply a scan pulse to the plurality of gate lines, and a bootstrap capacitor for preventing output loss of the scan pulses of the gate driver in the active area of the OLED display panel.

Abstract: The present disclosure relates to an OLED display panel for minimizing the size of a bezel and includes: an active area including data lines, scan lines intersecting the data lines, and sub-pixels arranged at each intersection; and a stage of a GIP driving circuit distributed and arranged in a plurality of unit pixel regions driven by m (m being a natural number) scan lines in the active area, to supply scan pulses to the corresponding scan lines, wherein the active area further includes m GIP internal connection lines parts respectively adjacent to the m scan lines, and a plurality of internal connection lines for connecting elements constituting each stage is distributed and arranged in the m GIP internal connection line parts.

Abstract: The present disclosure relates to an OLED display panel and an OLED display device in which a GIP driving circuit is arranged in an active area in order to minimize a bezel size and a GIP signal is applied to the GIP driving circuit arranged in the active area using a single-sided COF, and the OLED display panel includes: an active area including data lines, scan lines intersecting the data lines, and sub-pixels arranged at each intersection; stages of a GIP driving circuit distributed and arranged in a plurality of unit pixel regions corresponding to the scan lines in the active area to supply scan pulses to the scan lines; and a non-active area including a pad part, a link part and a LOG part, wherein the pad part includes a gate pad part for supplying various control signals to the stages of the GIP driving circuit, and a data pad part for supplying a data voltage to each data line, and wherein the non-active area includes a plurality of signal lines extended from the gate pad part via the link part to the

Abstract: Disclosed herein is an organic light emitting diode (OLED) display device including an OLED display panel including a non-active area and an active area, having a plurality of gate lines and a plurality of data lines disposed in the active area, and having a plurality of subpixels arranged at intersections between the gate lines and the data lines in a matrix, a gate driver disposed in the non-active area of the OLED display panel to supply a scan pulse to the plurality of gate lines, and a bootstrap capacitor for preventing output loss of the scan pulses of the gate driver in the active area of the OLED display panel.

Abstract: Disclosed herein are a gate driver including at least two output buffers to drive at least two gate lines and capable of reducing an output deviation of each output buffer, and a flat panel display device including the same. The gate driver includes a plurality of gate-in-panels (GIPs) for sequentially supplying scan signals to a plurality of gate lines. Each GIP includes one carry signal output unit and at least two scan signal output units to drive at least two gate lines, and the carry signal output unit includes a pull-up transistor controlled by a voltage of a first node, a pull-down transistor controlled by a voltage of a second node, and a boosting capacitor formed between gate and source electrodes of the pull-up transistor.

Abstract: A display panel and an OLED display device using the same are disclosed. The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines.

Abstract: An array substrate for a gate-in-panel (GIP)-type organic light-emitting diode (OLED) display device is provided. A plurality of circuit blocks are formed on gate circuit units and separated into pixel lines in which respective gate lines are disposed, and a plurality of clock lines formed in each of signal input units. Each of the signal input units includes at least one group. Each of the groups includes the plurality of clock lines. Each of the circuit blocks includes one or two partial circuit blocks, which are sequentially disposed in a row in a lengthwise direction of the gate line in each of the pixel lines. Each of the partial circuit blocks is included in a signal input unit disposed most adjacent thereto, and connected to a clock line formed in one group disposed most adjacent thereto through a plurality of first connection lines.

Abstract: An organic light emitting display device includes a panel driver and a display panel including a plurality of pixels having a pixel circuit, a first driving voltage terminal connected to the driving transistor, a light emitting element, a second driving voltage terminal connected to the light emitting element, and a capacitor connected between a gate and source electrode of the driving transistor, the panel driver to drive the pixel circuit in a data charging period in which a difference between a data and reference voltage is charged into the capacitor, and a light emitting period in which the driving transistor receives a first driving voltage from the first driving voltage terminal and is turned on according to the voltage charged into the capacitor during the data charging period, whereby a current is supplied to the light emitting element which thereby emits light.

Abstract: An organic light emitting display device includes a panel driver and a display panel including a plurality of pixels having a pixel circuit, a first driving voltage terminal connected to the driving transistor, a light emitting element, a second driving voltage terminal connected to the light emitting element, and a capacitor connected between a gate and source electrode of the driving transistor, the panel driver to drive the pixel circuit in a data charging period in which a difference between a data and reference voltage is charged into the capacitor, and a light emitting period in which the driving transistor receives a first driving voltage from the first driving voltage terminal and is turned on according to the voltage charged into the capacitor during the data charging period, whereby a current is supplied to the light emitting element which thereby emits light.

Abstract: Disclosed herein are signal transmission lines for an image display device and a method for wiring the same. The signal transmission lines include a plurality of control signal supply lines formed in a display panel in which at least one driving circuit is formed integrally with an image display region, such that the control signal supply lines are supplied with control signals for control of the driving circuit, respectively, and a plurality of control signal transmission lines formed in the display panel to cross the control signal supply lines and each electrically connected with at least one of the control signal supply lines, so as to transmit a corresponding one of the control signals to the driving circuit, wherein the control signal transmission lines have the same overlap areas with the control signal supply lines when they cross the control signal supply lines.

Abstract: Disclosed herein are signal transmission lines for an image display device and a method for wiring the same. The signal transmission lines include a plurality of control signal supply lines formed in a display panel in which at least one driving circuit is formed integrally with an image display region, such that the control signal supply lines are supplied with control signals for control of the driving circuit, respectively, and a plurality of control signal transmission lines formed in the display panel to cross the control signal supply lines and each electrically connected with at least one of the control signal supply lines, so as to transmit a corresponding one of the control signals to the driving circuit, wherein the control signal transmission lines have the same overlap areas with the control signal supply lines when they cross the control signal supply lines.