Abstract: A semiconductor package includes: a base substrate; an interposer disposed on the base substrate, wherein the interposer includes a plurality of recesses in a bottom surface thereof; a semiconductor chip disposed on the interposer; a plurality of interposer connection terminals between the interposer and the base substrate, wherein the plurality of interposer connection terminals electrically connect the interposer to the base substrate; and a first underfill layer disposed between the interposer and the base substrate, wherein the first underfill layer at least partially surrounds the plurality of interposer connection terminals, wherein the first underfill layer at least partially surrounds a side surface of each of the plurality of recesses and has a slope declining from the bottom surface of the interposer to a top surface of the base substrate.

Abstract: A semiconductor package includes: a buffer die; a first core die disposed on the buffer die; a second core die disposed on the first core die; a first non-conductive film (NCF) disposed between the first core die and the second core die and bonding the first core die and the second core die to each other; a first molding layer at least partially surrounding a side surface of the first core die; and a second molding layer surrounding the first NCF and the first molding layer, wherein the first core die, the second core die, and the buffer die are disposed on the second molding layer, wherein a side surface of the first molding layer and a side surface of the first NCF form a coplanar surface.

Abstract: A semiconductor package may include a substrate, a chip structure mounted on the substrate, and a first dummy structure attached to the chip structure. The chip structure may include a first semiconductor chip, a second dummy structure disposed at a side of the first semiconductor chip, and a mold layer enclosing the first semiconductor chip and the second dummy structure. A bottom surface of the first semiconductor chip, a bottom surface of the second dummy structure, and a bottom surface of the mold layer may be coplanar with each other.

Abstract: A semiconductor device includes a peripheral circuit structure including peripheral circuits on a substrate and first bonding pads electrically connected to the peripheral circuits and a cell array structure including memory cells on a semiconductor layer and second bonding pads electrically connected to the memory cells and bonded to the first bonding pads. The cell array structure includes a stacked structure including insulating layers and electrodes, an external connection pad on a surface of the semiconductor layer, a dummy pattern at a same level as the semiconductor layer relative to the substrate, and a photosensitive insulating layer on the semiconductor layer and the dummy pattern. A first thickness of a portion of the photosensitive insulating layer vertically overlapping the external connection pad is greater than a second thickness of another portion of the photosensitive insulating layer vertically overlapping the dummy pattern.

Abstract: A semiconductor device may include a first substrate including device and edge regions, a first insulating structure on the first substrate, first metal pads and first dummy pads at the uppermost end of the first insulating structure, a second insulating structure on the first insulating structure, second metal pads and second dummy pads at the lowermost end of the second insulating structure, a first interconnection structure in the first insulating structure, electrically connected to the first metal pads and electrically isolated from the first dummy pads, and a second interconnection structure in the second insulating structure, electrically connected to the second metal pads, and electrically isolated from the second dummy pads. Ones of the first metal pads may be in contact with respective ones of the second metal pads on the device region, and ones of the first dummy pads may be in contact with respective ones of the second dummy pads on the edge region.

Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

Abstract: The semiconductor package, includes: a package substrate; a substrate adhesive member on the package substrate; a plurality of semiconductor chips stacked on the substrate adhesive member and including first and second semiconductor chips; and a conductive connection member connecting the package substrate and the semiconductor chips, each of the semiconductor chips including a semiconductor chip body, a chip pad, an upper oxide layer comprised of a first material and covering an upper surface of the semiconductor chip body and exposing a portion of an upper surface of the chip pad, and a lower oxide layer comprised of a second material and covering a lower surface of the semiconductor chip body, wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip.

Abstract: A semiconductor package includes a package substrate and a plurality of sub-packages provided on the package substrate. Each of the plurality of sub-packages includes a semiconductor chip, an interposer provided adjacent to the semiconductor chip, the interposer including a plurality of first through-silicon vias, an encapsulator provided between the semiconductor chip and the interposer, and a redistribution layer provided on the interposer, the encapsulator and the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite the first surface and a plurality of chip pads provided on the first surface. The redistribution layer includes a plurality of redistribution pads and a horizontal wiring provided between the plurality of redistribution pads and the plurality of first through-silicon vias. The redistribution layer is provided on the second surface of the semiconductor substrate, and extends on the encapsulator and the interposer.

Abstract: A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.

Abstract: Provided is a semiconductor package including a first semiconductor chip provided on a package substrate, an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip, and a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip, wherein the interconnection substrate includes a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and wherein the passive device is electrically connected to the second semiconductor chip.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

Abstract: A semiconductor package includes an interposer, a first semiconductor chip attached onto the interposer, second semiconductor chips stacked on the first semiconductor chip, at least two heat sinks mounted on the interposer and spaced apart from the second semiconductor chips, and a molding layer surrounding the second semiconductor chips and the at least two heat sinks.

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.