Abstract: The present invention relates to a digital phase-locked loop (PLL) circuit producing an output pulse stream or clock pulses in phase with a reference clock input. The digital PLL circuit consumes reduced power during a phase error compensating operation. The digital PLL circuit of the present invention includes, inter alia, a phase comparator for detecting phase errors of an input signal and a feedback signal; a charge pump for sourcing and/or sinking current in response to control signals based on a phase error detected in the phase comparator; and a sensing circuit for detecting a simultaneous activation of the sourcing and the sinking of the charge pump and for generating a sensing signal corresponding to the simultaneous activation, whereby the phase comparator generates in response to the sensing signal the control signals to inactivate the sourcing and the sinking of the charge pump. The charge pump is also activated in response to the sensing signal.

Abstract: There is provided a level shift circuit which includes an input terminal for receiving a logic input signal changing between a first voltage and a reference voltage. An output terminal provides a logic output signal changing between a second voltage and the reference voltage. A pull-up transistor has a control electrode and a pair of controlled electrodes. The controlled electrodes are coupled between the second voltage and the output terminal. A pull-down transistor has a control electrode and a pair of controlled electrodes. The control electrode of the pull-down transistor is coupled to the input terminal, and the controlled electrodes of the pull-down transistor are coupled between the reference voltage and the output terminal. A charge/discharge circuit charges the control electrode of the pull-up transistor with the second voltage when the logic input signal is changed from the reference voltage to the first voltage.