Patents by Inventor Iniyan Soundappa Elango
Iniyan Soundappa Elango has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862215Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.Type: GrantFiled: August 27, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Sateesh Talasila, Chandrasekhar Mandalapu, Robert Douglas Cassel, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Srivatsan Venkatesan
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Patent number: 11715520Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells.Type: GrantFiled: April 5, 2021Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Robert Douglas Cassel, Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango
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Publication number: 20230069190Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Sateesh Talasila, Chandrasekhar Mandalapu, Robert Douglas Cassel, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Srivatsan Venkatesan
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Publication number: 20230018390Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: ApplicationFiled: September 13, 2022Publication date: January 19, 2023Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Patent number: 11514985Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: GrantFiled: April 5, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319592Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: ApplicationFiled: April 5, 2021Publication date: October 6, 2022Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319594Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.Type: ApplicationFiled: May 25, 2022Publication date: October 6, 2022Inventors: Srivatsan Venkatesan, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319595Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells.Type: ApplicationFiled: April 5, 2021Publication date: October 6, 2022Inventors: Robert Douglas Cassel, Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango
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Publication number: 20220254999Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: February 28, 2022Publication date: August 11, 2022Inventors: Srivatsan VENKATESAN, Davide MANTEGAZZA, John GORMAN, Iniyan Soundappa ELANGO, Davide FUGAZZA, Andrea REDAELLI, Fabio PELLIZZER
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Patent number: 11348640Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.Type: GrantFiled: April 5, 2021Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventors: Srivatsan Venkatesan, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Patent number: 11327004Abstract: Systems and methods of using the same for functional fluorescence imaging of live cells in suspension with isotropic three dimensional (3D) diffraction-limited spatial resolution are disclosed. The method-live cell computed tomography (LCCT)-involves the acquisition of a series of two dimensional (2D) pseudo-projection images from different perspectives of the cell that rotates around an axis that is perpendicular to the optical axis of the imaging system. The volumetric image of the cell is then tomographically reconstructed.Type: GrantFiled: March 2, 2017Date of Patent: May 10, 2022Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Deirdre Meldrum, Roger Johnson, Laimonas Kelbauskas, Jeff Houkal, Brian Ashcroft, Dean Smith, Hong Wang, Shih-Hui Joseph Chao, Rishabh Shetty, Jakrey Myers, Iniyan Soundappa Elango
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Patent number: 11315292Abstract: Systems and methods of using the same for functional fluorescence imaging of live cells in suspension with isotropic three dimensional (3D) diffraction-limited spatial resolution are disclosed. The method-live cell computed tomography (LCCT)-in-volves the acquisition of a series of two dimensional (2D) pseudo-projection images from different perspectives of the cell that rotates around an axis that is perpendicular to the optical axis of the imaging system. The volumetric image of the cell is then tomographically reconstructed.Type: GrantFiled: March 2, 2018Date of Patent: April 26, 2022Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITYInventors: Deirdre Meldrum, Roger Johnson, Laimonas Kelbauskas, Jeff Houkal, Brian Ashcroft, Dean Smith, Hong Wang, Shih-Hui (Joseph) Chao, Rishabh Shetty, Jakrey Myers, Iniyan Soundappa Elango
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Patent number: 11264567Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.Type: GrantFiled: November 19, 2019Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Srivatsan Venkatesan, Davide Mantegazza, John Gorman, Iniyan Soundappa Elango, Davide Fugazza, Andrea Redaelli, Fabio Pellizzer
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Publication number: 20210151672Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: November 19, 2019Publication date: May 20, 2021Applicant: INTEL CORPORATIONInventors: SRIVATSAN VENKATESAN, DAVIDE MANTEGAZZA, JOHN GORMAN, INIYAN SOUNDAPPA ELANGO, DAVIDE FUGAZZA, ANDREA REDAELLI, FABIO PELLIZZER
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Publication number: 20200058140Abstract: Systems and methods of using the same for functional fluorescence imaging of live cells in suspension with isotropic three dimensional (3D) diffraction-limited spatial resolution are disclosed. The method-live cell computed tomography (LCCT)-in-volves the acquisition of a series of two dimensional (2D) pseudo-projection images from different perspectives of the cell that rotates around an axis that is perpendicular to the optical axis of the imaging system. The volumetric image of the cell is then tomographically reconstructed.Type: ApplicationFiled: March 2, 2018Publication date: February 20, 2020Inventors: Deirdre Meldrum, Roger Johnson, Laimonas Kelbauskas, Jeff Houkal, Brian Ashcroft, Dean Smith, Hong Wang, Shih-Hui (Joseph) Chao, Rishabh Shetty, Jakrey Myers, Iniyan Soundappa Elango
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Publication number: 20190346361Abstract: Systems and methods of using the same for functional fluorescence imaging of live cells in suspension with isotropic three dimensional (3D) diffraction-limited spatial resolution are disclosed. The method-live cell computed tomography (LCCT)-involves the acquisition of a series of two dimensional (2D) pseudo-projection images from different perspectives of the cell that rotates around an axis that is perpendicular to the optical axis of the imaging system. The volumetric image of the cell is then tomographically reconstructed.Type: ApplicationFiled: March 2, 2017Publication date: November 14, 2019Inventors: Deirdre Meldrum, Roger Johnson, Laimonas Kelbauskas, Jeff Houkal, Brian Ashcroft, Dean Smith, Hong Wang, Shih-Hui Joseph Chao, Rishabh Shetty, Jakrey Myers, Iniyan Soundappa Elango
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Patent number: 10391485Abstract: A microfluidic device useable for performing live cell computed tomography imaging is fabricated with a cover portion including a first wafer with at least one metal patterned thereon, a base portion including a second wafer with at least one metal patterned thereon and negative photoresist defining recesses therein, and a diffusive bonding layer including a negative photoresist arranged to join the cover portion and the base portion. A composition useful in live cell computer topography includes a long-chain polysaccharide at a concentration of from about 0.01% to about 10.0% in cell culture medium for supporting cell life while enabling cell rotation rate to be slowed to a speed commensurate with low light level imaging.Type: GrantFiled: September 25, 2014Date of Patent: August 27, 2019Assignee: ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA, ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITYInventors: Deirdre Meldrum, Roger Johnson, Iniyan Soundappa Elango, Andrew Shabilla, Hong Wang, Jakrey Myers, Laimonas Kelbauskas, Dean Smith, Pimwadee Limsirichai
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Publication number: 20150087007Abstract: A microfluidic device useable for performing live cell computed tomography imaging is fabricated with a cover portion including a first wafer with at least one metal patterned thereon, a base portion including a second wafer with at least one metal patterned thereon and negative photoresist defining recesses therein, and a diffusive bonding layer including a negative photoresist arranged to join the cover portion and the base portion. A composition useful in live cell computer topography includes a long-chain polysaccharide at a concentration of from about 0.01% to about 10.0% in cell culture medium for supporting cell life while enabling cell rotation rate to be slowed to a speed commensurate with low light level imaging.Type: ApplicationFiled: September 25, 2014Publication date: March 26, 2015Applicant: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of ArizInventors: Deirdre Meldrum, Roger Johnson, Iniyan Soundappa Elango, Andrew Shabilla, Hong Wang, Jakrey Myers, Laimonas Kelbauskas, Dean Smith, Pimwadee Limsirichai