Patents by Inventor In-June Choi

In-June Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240195017
    Abstract: A battery module includes: a battery cell assembly having a plurality of battery cells; a top plate configured to cover an upper side of the battery cell assembly; a bottom plate configured to cover a lower side of the battery cell assembly; a sensing assembly disposed to cover a front side and a rear side of the battery cell assembly; a pair of side plates disposed at side surfaces, respectively, of the battery cell assembly; and a pair of compression pads disposed between the pair of side plates and the battery cell assembly, respectively.
    Type: Application
    Filed: January 2, 2024
    Publication date: June 13, 2024
    Applicant: LG Energy Solution, Ltd.
    Inventors: Sung-Won Seo, Dong-Yeon Kim, Ho-June Chi, Dal-Mo Kang, Jin-Hak Kong, Jeong-O Mun, Yoon-Koo Lee, Yong-Seok Choi, Alexander Eichhorn, Andreas Track
  • Publication number: 20240170394
    Abstract: Integrated circuitry comprising an interconnect level with multi-height lines contacted by complementary multi-height vias. In some examples, a first line of a taller height is contacted by a first via of a shorter height while a second line of a shorter height is contacted by a second via of a taller height. The first and second vias and first and second lines may be subtractively defined concurrently from a same stack of conductive material layers such that the first via comprises a first conductive material layer, and the first line comprises second and third conductive material layers while the second via comprises the first and second conductive material layers and the second line comprises the third conductive material layer.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Applicant: Intel Corporation
    Inventors: Elijah Karpov, June Choi, Manish Chandhok, Miriam Reshotko, Matthew Metz
  • Publication number: 20240170698
    Abstract: Disclosed is a method of fuel cell analysis. The method includes measuring at least a portion of an electrode of a fuel cell to determine a measured result. The method also includes analyzing a state of the fuel cell according to the measured result.
    Type: Application
    Filed: December 20, 2022
    Publication date: May 23, 2024
    Applicant: HYUNDAI MOBIS CO., LTD.
    Inventors: Hyo June LEE, Jin Hwa LEE, Sung Chul LEE, Ju Ho SHIN, Kyung Jin LEE, Seung Kyu CHOI
  • Publication number: 20240170697
    Abstract: An apparatus for providing operation logic of a fuel cell system may include an activation part configured to perform activation on a fuel cell, and an operating performance part configured to perform constant current operation according to the performing of activation.
    Type: Application
    Filed: December 20, 2022
    Publication date: May 23, 2024
    Applicant: HYUNDAI MOBIS Co., Ltd.
    Inventors: Seung Kyu CHOI, Jin Hwa LEE, Hyo June LEE, Ju Ho SHIN, Kyung Jin LEE, Sung Chul LEE
  • Patent number: 11990940
    Abstract: Provided are a subminiature optical transmission module and a method for manufacturing same. The optical transmission module includes: a mold body having a first surface and a second surface opposite to each other; multiple edge-type light emitting elements, each of which is molded inside the mold body by fitting same to the first surface so as to match with the first surface and generates an optical signal in the edge direction of a chip; and an optical component disposed on one side thereof so as to optically multiplex multiple optical signals incident from the multiple edge-type light emitting elements and to output same, wherein the identical height is configured between the surface of each light emitting element and the optical axis of the optical component, and the edge direction of the chip is parallel to the first surface of the mold body.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 21, 2024
    Assignee: LIPAC CO., LTD.
    Inventors: Seong Wook Choi, Young June Park
  • Publication number: 20240145383
    Abstract: An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an example, the second ring structure is non-overlapping with the first ring structure. In an example, the first ring structure is above the first set of devices of the device layer, and the second ring structure is above the second set of devices of the device layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: Intel Corporation
    Inventors: June Choi, Keith E. Zawadzki, Kimberly L. Pierce, Mohammad Enamul Kabir
  • Publication number: 20240145672
    Abstract: Provided is a positive electrode active material which includes an inner region that is a region from the center of the positive electrode active material particle to R/2, and an outer region that is a region from R/2 to the surface of the positive electrode active material particle, wherein R is a distance from the center of the positive electrode active material particle to the surface thereof. The positive electrode active material further includes 25% to 80% of crystallites C with respect to a total number of crystallites in the outer region. The crystallites C have a high crystallite long-axis orientation degree of 0.5 to 1 and a low crystallite c-axis orientation degree less than 0.5. Thus, the positive electrode active material has high capacity characteristics and a small amount of gas generated.
    Type: Application
    Filed: March 22, 2022
    Publication date: May 2, 2024
    Applicant: LG Chem, Ltd.
    Inventors: Won Sig Jung, Hwan Young Choi, Jong Pil Kim, Yeo June Yoon, Kang Hyeon Lee, Tae Young Rhee, Yong Jo Jung
  • Publication number: 20240143927
    Abstract: Provided are a method for generating a summary and a system therefor. The method according to some embodiments may include calculating a likelihood loss for a summary model using a first text sample and a first summary sentence corresponding to the first text sample, calculating an unlikelihood loss for the summary model using a second text sample and the first summary sentence, the second text sample being a negative sample generated from the first text sample, and updating the summary model based on the likelihood loss and the unlikelihood loss.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Applicants: SAMSUNG SDS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Sung Roh YOON, Bong Kyu HWANG, Ju Dong KIM, Jae Woong YUN, Hyun Jae LEE, Hyun Jin CHOI, Jong Yoon SONG, Noh II PARK, Seong Ho JOE, Young June GWON
  • Publication number: 20240105589
    Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Shao Ming Koh, Patrick Morrow, June Choi, Sukru Yemenicioglu, Nikhil Jasvant Mehta
  • Patent number: 11942279
    Abstract: A tantalum capacitor includes a tantalum body comprising a tantalum sintered body containing tantalum powder, a conductive polymer layer disposed on the tantalum sintered body and including a first filler as a non-conductive particle, and a tantalum wire. The first filler includes a core including at least one metal oxide among BaTiO3, Al2O3, SiO2 and ZrO2, and a coating film disposed on a surface of the core.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Ho Hong, Young Seuck Yoo, Hee Sung Choi, Young June Lee
  • Publication number: 20240096785
    Abstract: An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: Intel Corporation
    Inventors: June Choi, Charles Henry Wallace, Richard E. Schenker, Nikhil Jasvant Mehta
  • Patent number: 11934950
    Abstract: An apparatus for embedding a sentence feature vector according to an embodiment includes a sentence acquisitor configured to acquire a first sentence and a second sentence, each including one or more words; a vector extractor configured to extract a first feature vector corresponding to the first sentence and a second feature vector corresponding to the second sentence by independently inputting each of the first sentence and the second sentence into a feature extraction network; and a vector compressor configured to compress the first feature vector and the second feature vector into a first compressed vector and a second compressed vector, respectively, by independently inputting each of the first feature vector and the second feature vector into a convolutional neural network (CNN)-based vector compression network.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Seong Ho Joe, Young June Gwon, Seung Jai Min, Ju Dong Kim, Bong Kyu Hwang, Jae Woong Yun, Hyun Jae Lee, Hyun Jin Choi
  • Publication number: 20240088379
    Abstract: Provided is a positive electrode active material which includes an inner region that is a region from the center of the positive electrode active material particle to R/2; and an outer region that is a region from R/2 to the surface of the positive electrode active material particle, wherein R is a distance from the center of the positive electrode active material particle to the surface thereof. The positive electrode active material further includes 30% to 80% of crystallites A with respect to a total number of crystallites in the outer region of the positive electrode active material, the crystallites A having high crystallite long-axis orientation degree and crystallite c-axis orientation degree. Thus, the positive electrode active material can achieve excellent capacity characteristics and service life characteristics.
    Type: Application
    Filed: March 22, 2022
    Publication date: March 14, 2024
    Applicant: LG Chem, Ltd.
    Inventors: Won Sig Jung, Hwan Young Choi, Jong Pil Kim, Yeo June Yoon, Kang Hyeon Lee, Tae Young Rhee, Yong Jo Jung
  • Publication number: 20240088177
    Abstract: An image sensing device is provided to include a pixel array having a plurality of pixels arranged in a matrix shape. Each of the pixels includes: a control node configured to generate a hole current in a substrate; a detection node configured to capture photocharge migrated by the hole current, formed in a shape whose at least part is partially open, and disposed to surround the control node, and a low resistance region including a dielectric layer formed in the substrate, and disposed in the opening on of the detection node. The low resistance region includes an inner low resistance region disposed between the control node and the center of the pixel.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Hyung June YOON, Jong Eun KIM, Jong Chae KIM, Jae Won LEE, Jae Hyung JANG, Hoon Moo CHOI
  • Patent number: 11923562
    Abstract: A battery module includes: a battery cell assembly having a plurality of battery cells; a top plate configured to cover an upper side of the battery cell assembly; a bottom plate configured to cover a lower side of the battery cell assembly; a sensing assembly disposed to cover a front side and a rear side of the battery cell assembly; a pair of side plates disposed at side surfaces, respectively, of the battery cell assembly; and a pair of compression pads disposed between the pair of side plates and the battery cell assembly, respectively.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: March 5, 2024
    Assignee: LG Energy Solution, Ltd.
    Inventors: Sung-Won Seo, Dong Yeon Kim, Ho-June Chi, Dal-Mo Kang, Jin-Hak Kong, Jeong-O Mun, Yoon-Koo Lee, Yong-Seok Choi, Alexander Eichhorn, Andreas Track
  • Publication number: 20240071913
    Abstract: An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: June Choi, Richard Schenker, Charles H. Wallace, Nikhil J. Mehta, Clifford L. Ong
  • Publication number: 20230420512
    Abstract: Integrated circuit structures having backside power staple are described. In an example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts is extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A front-side metal routing layer is extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts. A backside metal routing layer is extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer. A conductive feedthrough structure couples the backside metal routing layer to the front-side metal routing layer.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Sukru YEMENICIOGLU, Xinning WANG, Nischal ARKALI RADHAKRISHNA, Leonard P. GULER, Mauro J. KOBRINSKY, June CHOI, Pratik PATEL, Tahir GHANI
  • Publication number: 20230347555
    Abstract: A shaping apparatus for a pouch-shaped battery case includes a punch configured to press a laminate sheet in order to shape an electrode assembly receiving portion of the pouch-shaped battery case, a die in which an accommodation portion is formed having a size corresponding to the electrode assembly receiving portion, a holder configured to fix an outer periphery of the laminate sheet, and an electromagnetic field-generating means attached to the punch and configured to generate an electromagnetic field. A pouch-shaped battery case shaping process uses the shaping apparatus to manufacture the pouch-shaped battery case.
    Type: Application
    Filed: October 13, 2021
    Publication date: November 2, 2023
    Applicant: LG Energy Solution, Ltd.
    Inventors: Ho June Chi, Hang June Choi, Jeong Oh Moon, Jin Yong Park
  • Patent number: 11777157
    Abstract: Disclosed is a battery module including a module housing capable of effectively increasing an energy density while improving the heat dissipation efficiency. The battery module includes a cell assembly having a plurality of secondary batteries; and a module housing having at least one sidewall to accommodate the cell assembly in an inner space defined by the sidewall and having a cooling channel embedded in the sidewall.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 3, 2023
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Eun-Ah Ju, Hang-June Choi, Sung-Won Seo, Dal-Mo Kang, Jeong-O Mun, Yoon-Koo Lee
  • Patent number: 11745462
    Abstract: An optical adhesive sheet having an excellent repulsion resistance and an excellent swelling rate, and a method for manufacturing the same.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: September 5, 2023
    Inventors: Ae-Jung Jang, Hong-June Choi, Jang-Soon Kim