Abstract: A direct memory access controller (DMAC) for improving data transmission efficiency in multi-media over internet protocol (MMoIP) and a method therefor are provided. The DMAC requests and obtains a bus control right by determining that a DMA request signal is generated not only when a DMA request signal of a module for processing data in MMoIP is received but also when an operation of a timer operating during a predetermined period set considering periodicity of data in MMoIP is completed. Thus, the time taken to request a bus control right in a conventional DMAC can be reduced, thereby improving data transmission efficiency in MMoIP.

Abstract: A signal processing technology achieved in a signal processing module, which is physically separate from a control module for controlling overall operations of a signal processing apparatus, is provided. Input of new data to a system memory is recognized. Upon the recognition of the input of the new data, the new data is read from the system memory. The new data read from the system memory is written to a local memory. Data sharing between software and hardware is effectively achieved in a system for performing a wideband codec processing using a dedicated hardware.

Abstract: A direct memory access controller (DMAC) for improving data transmission efficiency in multi-media over internet protocol (MMoIP) and a method therefor are provided. The DMAC requests and obtains a bus control right by determining that a DMA request signal is generated not only when a DMA request signal of a module for processing data in MMoIP is received but also when an operation of a timer operating during a predetermined period set considering periodicity of data in MMoIP is completed. Thus, the time taken to request a bus control right in a conventional DMAC can be reduced, thereby improving data transmission efficiency in MMoIP.

Abstract: A DMA controller includes a channel status generator determining whether the state of a channel connected to a peripheral corresponds to the first part of transmission data when receiving a DMA request from the peripheral; an address generator generating addresses of the peripheral and a memory; a control signal generator generating signals representing DMA operation states; and a buffer temporarily storing data from the peripheral and transmitting them to the memory. The address generator generates an address of a register storing a data transmission size of the peripheral when the channel state represents the first part of the data. The control signal generator generates a control signal for receiving a value stored in the register storing the data transmission size.

Abstract: A two-step combustion system configured to install an auxiliary combustion chamber at the upper lateral surface of the combustion chamber and to store some of the compressed fuel-air mixture in the auxiliary combustion chamber to allow the fuel-air mixture to be burnt again after the middle of an explosion stroke, thereby reducing the fluctuation range of the rotational force of a crankshaft.

Abstract: A two-step combustion system configured to install an auxiliary combustion chamber at the upper lateral surface of the combustion chamber and to store some of the compressed fuel-air mixture in the auxiliary combustion chamber to allow the fuel-air mixture to be burnt again after the middle of an explosion stroke, thereby reducing the fluctuation range of the rotational force of a crankshaft.