Patents by Inventor Inna Patrick
Inna Patrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180374888Abstract: A photodiode (PD) of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a top PD of a second type disposed in a first-type layer; and a bottom PD of the second type disposed in the first-type layer and below the top PD, the bottom PD including at least one sub-photodiode (sub-PD) of the second type connected to the top PD and at least one sub-well of the first type surrounded by the at least one sub-PD.Type: ApplicationFiled: June 21, 2017Publication date: December 27, 2018Inventors: Yang Wu, Inna Patrick
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Patent number: 10163965Abstract: A photodiode (PD) of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a top PD of a second type disposed in a first-type layer; and a bottom PD of the second type disposed in the first-type layer and below the top PD, the bottom PD including at least one sub-photodiode (sub-PD) of the second type connected to the top PD and at least one sub-well of the first type surrounded by the at least one sub-PD.Type: GrantFiled: June 21, 2017Date of Patent: December 25, 2018Assignee: Himax Imaging LimitedInventors: Yang Wu, Inna Patrick
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Patent number: 9653513Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor includes an implant region of a second type formed in a crystalline layer of a first type. A channel of a transfer gate entirely covers the implant region, which partially joins a photodiode, a doped well and a floating diffusion node.Type: GrantFiled: April 8, 2016Date of Patent: May 16, 2017Assignee: Himax Imaging LimitedInventors: Yang Wu, Inna Patrick, Desmond Cheung, Kihong Kim, Feixia Yu
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Patent number: 9153621Abstract: A process of forming a back side illumination (BSI) image sensor is disclosed. An n-type implant is formed in a semiconductor substrate, and a p-type implant region, surrounding n-type in each pixel, is formed in the n-type implant such that in cross sectional view an n-type implant region is sandwiched between the two p-type implant regions. A transfer gate is formed on the semiconductor substrate such that the transfer gate entirely covers the n-type implant region and at least partially covers each of the p-type implant regions. A floating diffusion is formed in one of the p-type implant regions.Type: GrantFiled: September 2, 2014Date of Patent: October 6, 2015Assignee: Himax Imaging, Inc.Inventors: Yang Wu, Inna Patrick
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Patent number: 9070802Abstract: The present invention provides an image sensor and a fabricating method of the image sensor. The image sensor comprises: a first type epitaxial layer, a photodiode region, a first type well region, a gate region of a source follower transistor, and a first type implant isolation region. The first type well region is formed within the first type epitaxial layer with a first horizontal distance to the photodiode region and a vertical distance to a surface of the first type epitaxial layer. The gate region of a source follower transistor is formed on the surface of the first type epitaxial layer and above the first type well region, and has a second horizontal distance to the photodiode region. There is a distance between the first type implant isolation region and the first type well region as an anti-blooming path.Type: GrantFiled: March 12, 2014Date of Patent: June 30, 2015Assignee: Himax Imaging, Inc.Inventors: Yang Wu, Feixia Yu, Inna Patrick, Yu Hin Desmond Cheung
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Publication number: 20150048466Abstract: The present invention provides an image sensor and a fabricating method of the image sensor. The image sensor comprises: a first type epitaxial layer, a photodiode region, a first type well region, a gate region of a source follower transistor, and a first type implant isolation region. The first type well region is formed within the first type epitaxial layer with a first horizontal distance to the photodiode region and a vertical distance to a surface of the first type epitaxial layer. The gate region of a source follower transistor is formed on the surface of the first type epitaxial layer and above the first type well region, and has a second horizontal distance to the photodiode region. There is a distance between the first type implant isolation region and the first type well region as an anti-blooming path.Type: ApplicationFiled: March 12, 2014Publication date: February 19, 2015Applicant: Himax Imaging, Inc.Inventors: Yang Wu, Feixia Yu, Inna Patrick, Yu Hin Desmond Cheung
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Publication number: 20140370642Abstract: A process of forming a back side illumination (BSI) image sensor is disclosed. An n-type implant is formed in a semiconductor substrate, and a p-type implant region, surrounding n-type in each pixel, is formed in the n-type implant such that in cross sectional view an n-type implant region is sandwiched between the two p-type implant regions. A transfer gate is formed on the semiconductor substrate such that the transfer gate entirely covers the n-type implant region and at least partially covers each of the p-type implant regions. A floating diffusion is formed in one of the p-type implant regions.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Inventors: YANG WU, INNA PATRICK
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Patent number: 7847366Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.Type: GrantFiled: March 11, 2009Date of Patent: December 7, 2010Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Inna Patrick, Richard A. Mauritzson
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Patent number: 7829368Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.Type: GrantFiled: February 20, 2009Date of Patent: November 9, 2010Assignee: Aptina Imaging CorporationInventor: Inna Patrick
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Patent number: 7768047Abstract: An imager element, device and imaging system image sensor pixel. The image sensor pixel includes a collection region, a floating diffusion region, and a transfer transistor having a recessed gate. The recessed gate is configured to couple the collection region to the floating diffusion region so that collected charge is transferred during activation. The recessed gate has an effective gate length greater than a physical gate length.Type: GrantFiled: May 10, 2007Date of Patent: August 3, 2010Assignee: Micron Technology, Inc.Inventors: Richard A. Mauritzson, Inna Patrick
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Patent number: 7749798Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.Type: GrantFiled: March 31, 2005Date of Patent: July 6, 2010Assignee: Aptina Imaging CorporationInventors: Howard E. Rhodes, Richard A. Mauritzson, Inna Patrick
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Patent number: 7718459Abstract: The exemplary embodiments provide an imager with dual conversion gain charge storage and thus, improved dynamic range. A dual conversion gain element (e.g., Schottky diode) is coupled between a floating diffusion region and a respective capacitor. The dual conversion gain element switches in the capacitance of the capacitor, in response to charge stored at the floating diffusion region, to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In an additional aspect, the exemplary embodiments provide an ohmic contact between the gate of a source follower transistor and the floating diffusion region which assists in the readout of the dual conversion gain output signal of a pixel.Type: GrantFiled: April 15, 2005Date of Patent: May 18, 2010Assignee: Aptina Imaging CorporationInventors: Inna Patrick, Sungkwon C. Hong, Jeffrey A. McKee
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Patent number: 7704782Abstract: Imager devices having an array of photosensors, each photosensor having at least two doped regions. The two doped regions are each independently tailored to a particular wavelength.Type: GrantFiled: August 30, 2005Date of Patent: April 27, 2010Assignee: Aptina Imaging CorporationInventors: John Ladd, Inna Patrick, Gennadiy A. Agranov, Jeff A. McKee
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Patent number: 7687832Abstract: A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first charge storage region and between the first storage region and a floating diffusion region. A global shutter gate is formed to control the charge barrier and transfer charges from the photodiode to the first charge storage region by effectively lowering the first charge barrier. A transfer transistor acts to transfer charges from the first storage region to the floating diffusion region by reducing the second charge barrier.Type: GrantFiled: September 7, 2006Date of Patent: March 30, 2010Assignee: Aptina Imaging CorporationInventors: Inna Patrick, Sungkwon C. Hong
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Patent number: 7635604Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.Type: GrantFiled: April 14, 2005Date of Patent: December 22, 2009Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Inna Patrick, Richard A. Mauritzon
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Publication number: 20090173975Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.Type: ApplicationFiled: March 11, 2009Publication date: July 9, 2009Inventors: Howard E. Rhodes, Inna Patrick, Richard A. Mauritzson
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Publication number: 20090162964Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.Type: ApplicationFiled: February 20, 2009Publication date: June 25, 2009Inventor: Inna Patrick
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Patent number: 7511354Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.Type: GrantFiled: December 11, 2006Date of Patent: March 31, 2009Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Inna Patrick, Richard A. Mauritzson
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Patent number: 7510900Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.Type: GrantFiled: October 6, 2006Date of Patent: March 31, 2009Assignee: Aptina Imaging CorporationInventor: Inna Patrick
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Patent number: 7495273Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.Type: GrantFiled: July 27, 2004Date of Patent: February 24, 2009Assignee: Aptina Imaging CorporationInventor: Inna Patrick