Patents by Inventor Innocenzo Tortorelli

Innocenzo Tortorelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE DIMENSIONAL MEMORY ARRAYS
    Publication number: 20190378877
    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
    Type: Application
    Filed: August 26, 2019
    Publication date: December 12, 2019
    Inventors: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
  • Method, system, and device for L-shaped memory component
    Patent number: 10497863
    Abstract: Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. A storage cell may further comprise a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli
  • Three dimensional memory array
    Patent number: 10497753
    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli
  • TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
    Publication number: 20190362789
    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
  • THREE DIMENSIONAL MEMORY ARRAY
    Publication number: 20190341425
    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli
  • Three dimensional memory arrays
    Patent number: 10461125
    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
  • APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME
    Publication number: 20190325957
    Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 24, 2019
    Inventors: Innocenzo Tortorelli, Stephen Tang, Christina Papagianni
  • SET TECHNIQUE FOR PHASE CHANGE MEMORY
    Publication number: 20190324671
    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
  • Apparatuses including multi-level memory cells and methods of operation of same
    Patent number: 10446226
    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
  • APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME
    Publication number: 20190295636
    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
  • Programming enhancement in self-selecting memory
    Patent number: 10424374
    Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli, Fabio Pellizzer
  • CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    Publication number: 20190288194
    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 19, 2019
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Andrea Ghetti
  • Apparatuses and methods including memory and operation of same
    Patent number: 10418102
    Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Stephen Tang, Christina Papagianni
  • DOPANT-MODULATED ETCHING FOR MEMORY DEVICES
    Publication number: 20190252612
    Abstract: Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Inventors: Innocenzo Tortorelli, Mattia Robustelli
  • Apparatuses and methods including memory and operation of same
    Patent number: 10381077
    Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Stephen Tang, Christina Papagianni
  • DRIFT MITIGATION WITH EMBEDDED REFRESH
    Publication number: 20190206506
    Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
    Type: Application
    Filed: February 25, 2019
    Publication date: July 4, 2019
    Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
  • MULTI-LEVEL SELF-SELECTING MEMORY DEVICE
    Publication number: 20190189203
    Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
    Publication number: 20190189206
    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
  • APPARATUSES AND METHODS OF READING MEMORY CELLS
    Publication number: 20190180817
    Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Inventors: Innocenzo Tortorelli, Fabio Pellizzer, Ferdinando Bedeschi
  • METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT CROSS REFERENCES
    Publication number: 20190181340
    Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 13, 2019
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli