Abstract: A combined binary and binary coded decimal (BCD) arithmetic logic unit (binary/BCD ALU) having a binary adder adapted to perform decimal operations on BCD data without impacting the performance of binary operations. The combined binary/BCD ALU has a look-ahead carry binary adder for generating the binary sum or logical combination of inputs to the binary adder to an output (Y), the Y output being arranged in groups of four bits. The binary adder additionally provides carry outputs Co.sub.i of the binary additions from each of the groups of four bits of the Y output. A decimal correction unit, responsive to the Y and Co.sub.i outputs from the binary adder [ALU means], corrects the binary sum from the binary adder when performing BCD arithmetic. A multiplexer selects the Y output from the binary adder to a result output when performing operations on binary data. Alternately, the multiplexer selects the output from the decimal correction unit to the result output performing operations on BCD data.

Abstract: A 32-bit adder utilizes an optimal partitioning scheme for improving the 32-bit carry look-ahead. Instead of relying on the powers-of-four partitioning scheme used in prior art adders, the inventive technique uses "double generate" and "double propagate" terms. These represent the generate and propagate functions for two bits. In addition, "double group geneate" and "double group propagate" terms are produced, which represent the generate and propagate terms for a 8-bit groups. In this manner, a partition of 1-bit/8-bit is obtained, rather than the prior art 1-bit/4-bit/16-bit. The critical path is typically shortened from 7 logic levels to 5 logic levels, resulting in faster operation. The double functions are advantageously implemented using logic circuitry having two (or more) outputs per gate.

Abstract: In MOS logic circuits with a non-complementary circuit structure (for example, dynamic CMOS), a prior art logic gate generated only a single output signal. However, the logic tree often implements multiple functions, with one function being contained within another function. With prior art logic, if two or more of these functions are needed as separate available output signals, they have to be implemented in several separate gates. The present invention utilizes intermediate functions within the logic tree, providing gates having multiple outputs. Therefore, the present invention reduces the replication of circuitry, thus reducing circuit device count. The advantages include reduced integrated circuit chip area, speed improvement, and power savings, due to the reduction of device count and the corresponding reduction in wire lengths and output loading, etc.