Patents by Inventor Insik Jin
Insik Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7881104Abstract: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.Type: GrantFiled: December 2, 2008Date of Patent: February 1, 2011Assignee: Seagate Technology LLCInventors: Yong Lu, Hongyue Liu, Zheng Gao, Insik Jin, Dimitar V. Dimitrov
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Patent number: 7875923Abstract: A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual layers or as compositionally graded materials.Type: GrantFiled: May 15, 2008Date of Patent: January 25, 2011Assignee: Seagate Technology LLCInventors: Wei Tian, Insik Jin, Dimitar V. Dimitrov, Song S. Xue
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Publication number: 20110007546Abstract: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Nurul Amin, Insik Jin, Venugopalan Vaithyanathan, Wei Tian, YoungPil Kim
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Publication number: 20110007544Abstract: A non-volatile memory cell and method of use therefore are disclosed. In accordance with various embodiments, the memory cell comprises a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region comprises an active interface region disposed between a first tunneling barrier and a second tunneling barrier. A high resistive film is formed in the active interface region with migration of ions from both the metal and conducting regions responsive to a write current to program the memory cell to a selected resistive state.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Venugopalan Vaithyanathan, Markus Jan Peter Siegert, Wei Tian, Muralikrishnan Balakrishnan, Insik Jin
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Publication number: 20110006276Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Young Pil Kim, Nurul Amin, Dadi Setiadi, Venugopalan Vaithyanathan, Wei Tian, Insik Jin
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Publication number: 20110007545Abstract: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Insik Jin, YoungPil Kim, Ming Sun, Chulmin Jung, Venugopalan Vaithyanathan, Nurul Amin, Wei Tian, Yong Lu
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Publication number: 20110007548Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
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Publication number: 20110007581Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: Seagate Technology LLCInventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
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Publication number: 20110007551Abstract: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Wei Tian, Insik Jin, Venugopalan Vaithyanathan, Haiwen Xi, Michael Xuefei Tang, Brian Lee
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Publication number: 20110002161Abstract: A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array.Type: ApplicationFiled: July 6, 2009Publication date: January 6, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Insik Jin, Nurul Amin, Wei Tian, Young Pil Kim, Venugopalan Vaithyanathan, Ming Sun, Chulmin Jung
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Publication number: 20100277969Abstract: A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; and a second electrode having a lower portion, an upper portion and an outer surface; wherein the outer surface of the resistive layer directly contacts the inner surface of the first electrode.Type: ApplicationFiled: July 14, 2010Publication date: November 4, 2010Applicant: SEAGATE TECHNOLOGY LLC.Inventors: Shaoping Li, Insik Jin, Zheng Gao, Eileen Yan, Kaizhong Gao, Haiwen Xi, Song Xue
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Patent number: 7800941Abstract: A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set.Type: GrantFiled: November 18, 2008Date of Patent: September 21, 2010Assignee: Seagate Technology LLCInventors: Young Pil Kim, Chulmin Jung, Hyung-Kew Lee, Insik Jin, Michael Xuefei Tang
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Patent number: 7795606Abstract: Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.Type: GrantFiled: October 30, 2008Date of Patent: September 14, 2010Assignee: Seagate Technology LLCInventors: Insik Jin, Yang Li, Dadi Setiadi, Song S. Xue
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Patent number: 7791925Abstract: A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; and a second electrode having a lower portion, an upper portion and an outer surface; wherein the outer surface of the resistive layer directly contacts the inner surface of the first electrode.Type: GrantFiled: October 31, 2008Date of Patent: September 7, 2010Assignee: Seagate Technology, LLCInventors: Shaoping Li, Insik Jin, Zheng Gao, Eileen Yan, Kaizhong Gao, Haiwen Xi, Song Xue
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Publication number: 20100220512Abstract: Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source which uses an array of resistive sense memory cells, such as but not limited to STRAM or RRAM cells, to provide a controlled power bias to a load, such as but not limited to a micro-oscillator. In some embodiments, the programmable power source incorporates an array of serially connected resistive sense memory cells. A selectively controllable power level is applied by the programmable power source to a load in relation to a control input which selectively programs at least selected ones of the memory cells to a selected resistance state.Type: ApplicationFiled: March 2, 2009Publication date: September 2, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Yiran Chen, Insik Jin, Hai Li, Dimitar V. Dimitrov, Dexin Wang
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Publication number: 20100207219Abstract: A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.Type: ApplicationFiled: February 17, 2009Publication date: August 19, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Insik Jin, Hongyue Liu, Yong Lu, Xiaobin Wang
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Publication number: 20100193761Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.Type: ApplicationFiled: January 30, 2009Publication date: August 5, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Nurul Amin, Insik Jin, Wei Tian, Andrew James Wirebaugh, Venugopalan Vaithyanathan, Ming Sun
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Publication number: 20100182837Abstract: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Insik Jin, Yang Li, Hongyue Liu, Song S. Xue
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Patent number: 7750386Abstract: A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.Type: GrantFiled: November 12, 2008Date of Patent: July 6, 2010Assignee: Seagate Technology LLCInventors: Wei Tian, Venkatram Venkatasamy, Ming Sun, Michael Xuefei Tang, Insik Jin, Dimitar V. Dimitrov
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Publication number: 20100135061Abstract: In some embodiments of the invention a non-volatile memory cell is provided with a first electrode, a second electrode, and one or more side layers of a ferroelectric metal oxide and a ferroelectric material layer between the first and second electrodes. The ferroelectric material layer may be provided between, e.g., adjacent, two side layers of a ferroelectric metal oxide or between a single layer of a ferroelectric metal oxide and an electrode. The ferroelectric metal oxide may in some cases include a uniform layered structure such as a bismuth layer-structured ferroelectric material like Bi4Ti3O12. In some embodiments, the ferroelectric material layer is formed at least partially from PbZrxTi1-xO3. A non-volatile memory array including such memory cells is also provided.Type: ApplicationFiled: December 2, 2008Publication date: June 3, 2010Inventors: Shaoping Li, Kaizhong Gao, Insik Jin, Song Xue, Haiwen Xi, Zheng Gao, Eileen Yan