Patents by Inventor In-su Choi

In-su Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915782
    Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Min Lee, Nam Hyung Kim, Dae Jeong Kim, Do Han Kim, Min Su Kim, Deok Ho Seo, Won Jae Shin, Yong Jun Yu, Il Gyu Jung, In Su Choi
  • Patent number: 11631443
    Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 18, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Jun Yu, Nam Hyung Kim, Do-Han Kim, Min Su Kim, Deok Ho Seo, Won Jae Shin, Chang Min Lee, Il Gyu Jung, In Su Choi
  • Patent number: 11531585
    Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: December 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok Ho Seo, Nam Hyung Kim, Dae-Jeong Kim, Do-Han Kim, Min Su Kim, Won Jae Shin, Yong Jun Yu, Chang Min Lee, Il Gyu Jung, In Su Choi
  • Publication number: 20220215866
    Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.
    Type: Application
    Filed: September 21, 2021
    Publication date: July 7, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong Jun YU, Nam Hyung KIM, Do-Han KIM, Min Su KIM, Deok Ho SEO, Won Jae SHIN, Chang Min LEE, Il Gyu JUNG, In Su CHOI
  • Publication number: 20220208237
    Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.
    Type: Application
    Filed: August 20, 2021
    Publication date: June 30, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chang Min LEE, Nam Hyung KIM, Dae Jeong KIM, Do Han KIM, Min Su KIM, Deok Ho SEO, Won Jae SHIN, Yong Jun YU, Il Gyu JUNG, In Su CHOI
  • Publication number: 20210373996
    Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.
    Type: Application
    Filed: February 17, 2021
    Publication date: December 2, 2021
    Inventors: Deok Ho Seo, Nam Hyung Kim, Dae-Jeong Kim, Do-Han Kim, Min Su Kim, Won Jae Shin, Yong Jun Yu, Chang Min Lee, Il Gyu Jung, In Su Choi
  • Patent number: 10692566
    Abstract: A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-Young Lim, In-Su Choi, Dimin Niu, In-Dong Kim
  • Patent number: 10684979
    Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
  • Patent number: 10613782
    Abstract: A data storage system includes: a storage device having a first storage and a physically separate second storage. A first core includes first data information related to first data to be written to the first storage, and a second core includes second data information related to second data to be written to the second storage. A shared memory is accessible by the first and second cores, and an emergency power system supplies backup power to the first and second cores when external power supplied to the data storage system is less than a minimum threshold operating power. When a write operation error of the second core is detected in a first mode, the first core writes the second data information to the first storage as third data information and writes the second data to the first storage as third data by referring to the second data information.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Uk Kim, In Su Choi
  • Patent number: 10496584
    Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
  • Publication number: 20190034107
    Abstract: A data storage system includes: a storage device having a first storage and a physically separate second storage. A first core includes first data information related to first data to be written to the first storage, and a second core includes second data information related to second data to be written to the second storage. A shared memory is accessible by the first and second cores, and an emergency power system supplies backup power to the first and second cores when external power supplied to the data storage system is less than a minimum threshold operating power. When a write operation error of the second core is detected in a first mode, the first core writes the second data information to the first storage as third data information and writes the second data to the first storage as third data by referring to the second data information.
    Type: Application
    Filed: April 4, 2018
    Publication date: January 31, 2019
    Inventors: Min Uk KIM, In Su CHOI
  • Publication number: 20180329850
    Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
    Type: Application
    Filed: March 9, 2018
    Publication date: November 15, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
  • Publication number: 20180144786
    Abstract: A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 24, 2018
    Inventors: Sun-Young LIM, In-Su CHOI, Dimin NIU, In-Dong KIM
  • Patent number: 9971549
    Abstract: In a method of operating a memory device, a first write command, a first write address, and first write data are received by a first memory device through a channel. The first write command, received by the first memory device, is sensed by a controller. The controller is connected to the channel and controls a second memory device. The first memory device and the second memory device are different types of memory devices. When the first write command is sensed by the controller, a first write log is generated using the first write address and the first write data. The first write log is stored into a buffer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-Hwan Oh, Yong-Jun Yu, In-Su Choi
  • Publication number: 20170344311
    Abstract: In a method of operating a memory device, a first write command, a first write address, and first write data are received by a first memory device through a channel. The first write command, received by the first memory device, is sensed by a controller. The controller is connected to the channel and controls a second memory device. The first memory device and the second memory device are different types of memory devices. When the first write command is sensed by the controller, a first write log is generated using the first write address and the first write data. The first write log is stored into a buffer.
    Type: Application
    Filed: April 19, 2017
    Publication date: November 30, 2017
    Inventors: DOO-HWAN OH, YONG-JUN YU, IN-SU CHOI
  • Patent number: 9298612
    Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Sang-Joon Hwang, Seung-Man Shin, In-Su Choi, Jung-Ho Jung
  • Patent number: 9069714
    Abstract: A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-Soo Yu, Jun-Jin Kong, Hyoung-Joon Kim, Joo-Young Hwang, In-Su Choi
  • Patent number: 8976615
    Abstract: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Sung Shin, Seung-Man Shin, In-Su Choi
  • Publication number: 20140143478
    Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 22, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Sung SHIN, Sang-Joon HWANG, Seung-Man SHIN, In-Su CHOI, Jung-Ho JUNG
  • Publication number: 20140078846
    Abstract: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.
    Type: Application
    Filed: August 20, 2013
    Publication date: March 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung SHIN, Seung-Man SHIN, In-Su CHOI