Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

Abstract: A breast cancer risk assessment method of a breast cancer risk assessment system using a mammography image according to an embodiment includes generating, by the breast cancer risk assessment system, assessment data including breast density information generated by measuring density of an assessment target breast from a mammography image of the assessment target breast, and breast pattern information generated by extracting a characteristic pattern of the assessment target breast from the mammography image, and calculating, by the breast cancer risk assessment system, a breast cancer occurrence risk degree of the assessment target breast by applying a preset weight to each of pieces of information included in the assessment data.

Abstract: An internal reference voltage generation device may include a cell array including a plurality of cells which provide reference voltages of different levels. Each of the plurality of cells may include one of a plurality of divider resistors included in a resistor string; a transmission gate configured to output a voltage of a divider node which is connected to the one divider resistor, in response to a select signal; and a unit decoder configured to provide the select signal to the transmission gate.

Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Abstract: An apparatus for measuring a bio-signal includes: a light source configured to emit light; an ultrasonic transducer configured to obtain a photoacoustic signal generated from an object; a photoacoustic coupler disposed in contact with the ultrasonic transducer and configured to direct the light transmitted from the light source to a scanner and to direct the photoacoustic signal generated from the object to the ultrasonic transducer; the scanner configured to reflect the light incident from the photoacoustic coupler to the object, and reflect the photoacoustic signal generated from the object to the photoacoustic coupler; a scanner controller configured to adjust a light incident position on the object by controlling the angle of the scanner; a light detector configured to obtain a light signal by detecting the light scattered or reflected from the object; and a processor configured to obtain bio-information based on the light signal and the photoacoustic signal.

Abstract: A display device includes: a base substrate; a first pixel electrode, a second pixel electrode, and a third pixel electrode arranged on the base substrate to be spaced apart from each other; a pixel defining film on the first pixel electrode, the second pixel electrode, and the third pixel electrode and including a first opening exposing the first pixel electrode, a second opening exposing the second pixel electrode and spaced apart from the first opening, and a third opening exposing the third pixel electrode and spaced apart from the first opening and the second opening; a first organic layer on the first pixel electrode exposed by the first opening; a second organic layer on the second pixel electrode exposed by the second opening; and a third organic layer on the third pixel electrode exposed by the third opening.

Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.

Abstract: A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.

Abstract: The present disclosure relates to an offset elimination operation of an internal operational amplifier of a data driving circuit and relates to a technique that applies different offset elimination methods for each position of an operational amplifier.

Abstract: A display device includes: a display panel; a first sound generator disposed on one surface of the display panel, where the first sound generator vibrates the display panel to output a first sound; and a first vibration damping member disposed between the display panel and the first sound generator, where the first vibration damping member reduces a vibration displacement of the display panel.

Abstract: Disclosed is a thermal conductivity measuring device including a sample fixing member that fixes a sample, an elastic member that presses the sample fixed to the sample fixing member downwards, and first auxiliary heat emitting part that is spaced apart from the sample fixing member upwards while the elastic member being interposed therebetween.

Abstract: A communication apparatus is provided to include an apparatus enclosure that includes a substrate seating surface and at least one or more connection grooves formed on the substrate seating surface, a first printed circuit board disposed on the substrate seating surface, a second printed circuit board disposed on the substrate seating surface on one side of the first printed circuit board, and at least one or more connectors disposed within the connection groove and configured to electrically connect the first printed circuit board and the second printed circuit board.

Abstract: The present disclosure relates to an electronic device, and more specifically, to an electronic device including a printed circuit board including a heat-generating element arranged on one surface thereof, and a heat transfer coin provided such that one surface of the heat transfer coin comes into contact with a portion of the other surface of the printed circuit board, opposite to the heat-generating element, so as to dissipate heat generated from the heat-generating element. Accordingly, the present disclosure provides an advantage of improving heat dissipation performance without increasing the thickness of the printed circuit board.

Abstract: The present invention relates to a signal shielding apparatus and an antenna apparatus including same, and in particular, comprises a shield cover which is stacked and disposed on a printed board assembly (hereinafter, abbreviated to “PBA”), in which a plurality of signal-related components are mounted on one side thereof to prevent leakage of a signal from the plurality of signal-related components, wherein a grooved shield cover seating groove is formed in one surface of the PBA, and an insertion end insertably seated in the shield cover seating groove is integrally formed in the other surface from among one surface and the other surface of the shield cover, the other surface facing the one surface of the PBA, thereby providing advantages in that an increase in the manufacturing cost may be prevented, EMI shielding may be facilitated, and heat dissipation performance may be significantly improved.

Abstract: Provided are a method for preparing a polyetherketoneketone and a polyetherketoneketone prepared thereby, wherein, at the time of a polymerization reaction, nitrogen gas is blown into a liquid reaction medium while stirring, thereby quickly removing hydrochloric acid, which is a by-product generated during the reaction, and preventing aggregation of resin particles, thus suppressing the generation of scales.

Abstract: A storage device, a non-volatile memory device, and a method of operating the non-volatile memory device are provided. The storage device includes a storage controller configured to send a command and program data including a pattern of one or more bits, a non-volatile memory device configured to receive the command and the program data, and a pattern monitoring circuit configured to monitor a pattern of the program data sent from the storage controller. The pattern monitoring circuit is configured to send an abnormal status check bit to the storage controller when the program data includes repeated patterns that are repeated a preset number of times or more, and the storage controller is configured to resend the program data to the non-volatile memory device in response to receiving the abnormal status check bit.

Abstract: An embodiment relates to a method of measuring an ambient temperature by using a temperature sensor provided in an integrated circuit (IC) and a measurement error of a temperature sensor may be improved by correcting an output value of a temperature sensor by using a correction value stored in a memory.

Abstract: The present embodiment relates to an oscillator circuit, a semiconductor integrated circuit device and a method for frequency correction of an oscillator circuit, and more particularly, to an oscillator circuit, a semiconductor integrated circuit device and a method for frequency correction of an oscillator circuit capable of stably maintaining an output frequency of a clock signal even when a temperature of the semiconductor integrated circuit device changes.

Abstract: A chip-on-film package includes plurality of bumps may be arranged on an integrated circuit, and a plurality of metallic lines are connected to the bumps, thereby transmitting data to a panel, and in a data driving apparatus which may be implemented as the integrated circuit, first bumps and second bumps may be arranged in the same direction in a staggered manner.

Abstract: A data storage device including: a memory device including a plurality of memory blocks; and a memory controller configured to control the memory device, wherein the plurality of memory blocks are connected with row lines, wherein the row lines include word lines, wherein the memory controller is further configured to: check whether a resistive defect occurs at the row lines except for the word lines; and set a program operation time of a memory block corresponding to a row line, at which the resistive defect occurs, to be longer than a program operation time of the other memory blocks.