Patents by Inventor INVENSAS CORPORATION
INVENSAS CORPORATION has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140313834Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: ApplicationFiled: April 23, 2013Publication date: October 23, 2014Applicant: Invensas CorporationInventor: Invensas Corporation
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Publication number: 20140273346Abstract: In a high volume method for manufacturing a microelectronic package, a spacer element and a first die, i.e., microelectronic element, can be attached face-down to a surface of a substrate, contacts on the first die facing a first through opening of the substrate. Then, a second die can be attached face-down atop the first die and the spacer element, contacts on the second die disposed beyond an edge of the first die and facing a second through opening in the substrate. Electrical connections can then be formed between each of the first and second dies and the substrate. The first and second dies can be transferred from positions of a single diced wafer which are selected to maximize compound speed bin yield of the microelectronic package.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventor: INVENSAS CORPORATION
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Publication number: 20140110832Abstract: A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package.Type: ApplicationFiled: March 15, 2013Publication date: April 24, 2014Applicant: INVENSAS CORPORATIONInventor: Invensas Corporation
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Publication number: 20140014894Abstract: High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.Type: ApplicationFiled: December 31, 2012Publication date: January 16, 2014Applicant: INVENSAS CORPORATIONInventor: INVENSAS CORPORATION
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Publication number: 20130224914Abstract: A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.Type: ApplicationFiled: January 29, 2013Publication date: August 29, 2013Applicant: INVENSAS CORPORATIONInventor: Invensas Corporation
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Publication number: 20130207249Abstract: Metal rerouting interconnects at one or more sides of a die or multiple die segments can form edge bonding pads for electrical connection. Insulation can be applied to surfaces of the die or multiple die segments after optional thinning and singulation, and openings can be made in the insulation to the electrical connection pads. After being placed atop one another in a stack, vertically adjacent die or die segments can be electrically interconnected using a flexible bond wire or bond ribbon attached to an electrical connection pad exposed within such opening, the bond wire or ribbon protruding horizontally, and an electrically conductive polymer, or epoxy, filaments or lines can be applied to the stack.Type: ApplicationFiled: December 27, 2012Publication date: August 15, 2013Applicant: INVENSAS CORPORATIONInventor: INVENSAS CORPORATION
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Publication number: 20130200533Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: ApplicationFiled: March 12, 2013Publication date: August 8, 2013Applicant: INVENSAS CORPORATIONInventor: Invensas Corporation
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Publication number: 20130186944Abstract: An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer.Type: ApplicationFiled: March 12, 2013Publication date: July 25, 2013Applicants: Tessera Interconnect Materials, Inc., INVENSAS CORPORATIONInventor: Invensas Corporation
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Publication number: 20130128674Abstract: A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.Type: ApplicationFiled: December 4, 2012Publication date: May 23, 2013Applicant: INVENSAS CORPORATIONInventor: INVENSAS CORPORATION
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Publication number: 20130120023Abstract: A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.Type: ApplicationFiled: January 4, 2013Publication date: May 16, 2013Applicant: Invensas CorporationInventor: Invensas Corporation
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Publication number: 20130119117Abstract: A bonding wedge particularly suitable for making wire off-die interconnects includes an aperture opening onto a notch or pocket adjacent to the rear of a foot. The foot includes a heel portion and a toe portion. When the bonding wedge is in use, a wire is fed from feedstock through the aperture and the notch or pocket, and passes beneath the foot and extends beyond the toe. The toe is configured to mitigate upward displacement of the free end of the wire during the bonding process.Type: ApplicationFiled: November 2, 2012Publication date: May 16, 2013Applicant: Invensas CorporationInventor: Invensas Corporation
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Publication number: 20130114235Abstract: An EMI shield can be formed directly on a component, e.g., an unpackaged or packaged semiconductor die, by depositing and curing a curable composition which includes electrically conductive particles and a carrier. In examples, the shield can be configured as a grid or net of electrically conductive traces or lines. The curable electrically conductive material may be applied to the component surface in a flowable form and cured or allowed to cure to form the electrically conductive shield. The shield can be electrically coupled to contacts on an underlying circuit panel or support. The coupling material may be a conductive adhesive, and may be or may include a material the same as, or similar to, the shield material.Type: ApplicationFiled: November 5, 2012Publication date: May 9, 2013Applicant: INVENSAS CORPORATIONInventor: Invensas Corporation
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Publication number: 20130083584Abstract: A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe.Type: ApplicationFiled: October 3, 2012Publication date: April 4, 2013Applicant: INVENSAS CORPORATIONInventor: INVENSAS CORPORATION