Abstract: In general, the invention facilitates searching for energy peaks in spread spectrum wireless communication systems with greater precision. More particularly, various embodiments of the invention may involve reporting not only an energy peak and its associated offset, but also the energy levels corresponding to one or more offsets occurring before and after the offset at which the energy peak occurs. Interpolation or extrapolation techniques may be used to predict the actual location of an energy peak based on the apparent location of the peak and the energy levels observed at surrounding offsets.

Abstract: A method and apparatus for reduced acquisition time are disclosed. In one embodiment, such as in a W-CDMA system, a receiver receives one or more signals from remote stations, each signal comprising a scrambling code associated with one of a plurality of code groups, each code group identified by a unique series of a synchronization codes. A searcher identifies a subset of first synchronization codes, and a processor selects one or more hypotheses in response to the received subset. The searcher may then perform searching for a scrambling code in accordance with the one or more hypotheses. The scrambling code search may be performed in parallel with continued synchronization code searching. Various other embodiments are also disclosed.

Abstract: In a real-time mode, a clock signal of a searcher architecture is disabled between synchronization sequence bursts. In a sample storage or asynchronous mode, portions of stored signals do not belong to any hypothesis to be tested (e.g. portions that occur between synchronization signal bursts) are not loaded into the searcher delay chain.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

Abstract: A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

Abstract: An integrated circuit for a modem processor includes processing units that are partitioned into “always-on” and “collapsible” power domains. An always-on power domain is powered on at all times. A collapsible power domain can be powered off if the processing units in the power domain are not needed. A power control unit within an always-on power domain powers down the collapsible power domains after going into sleep and powers up these domains after waking up from sleep. Tasks for powering down the collapsible power domains may include (1) saving pertinent hardware registers for these power domains, (2) freezing output pins of the IC to minimally disturb external units, (3) clamping input pins of the collapsed power domains, (4) powering down a main oscillator and disabling the oscillator clock, and so on. Complementary tasks are performed for powering up the collapsed power domains.

Abstract: Provided is a system and method for constructing a data message in a communications device including a processor configured to process sequentially transmitted messages. Each of the messages requires a predetermined number of data frames. The technique of the instant invention includes receiving portions of at least two of the transmitted messages in the processor. Each of the at least two received portions includes a subset of the predetermined number of data frames and excludes a remainder of the predetermined number of data frames. The subset of one of the received portions substantially matches the remainder of the other portion. Next, a determination is made as to whether a total number of the received subsets equals the predetermined number. Finally, a synthesized messaged is produced when the total number of the subsets is at least equal to the predetermined number. The synthesized message is formed of a combination of the subsets from each of the received portions.

Abstract: A method and device for converting at least one narrow band RF signal, being suitable for transmission between at least one communications device suitable for receiving wide-band RF signals and at least one base station, to baseband. The method includes directly down-converting a signal spectrum including the at least one RF narrow-band signal to baseband such that the at least one narrow-band RF signal results at a low intermediate frequency (IF). And, digitally phase rotating the down-converted signal spectrum such that the at least one narrow-band RF signal is phase rotated from the low-IF to baseband.

Abstract: A multi-carrier filter for a wireless communications system employing a multi-carrier signal. The multi-carrier filter includes a first mechanism for receiving the multi-carrier signal and extracting carrier signal components of the multi-carrier signal in response thereto. A second mechanism filters the carrier signal components and outputs a demodulated and filtered multi-bandwidth signal in response thereto. In the specific embodiment, the first mechanism includes a rotator. The multi-carrier signal is a 3× bandwidth multi-carrier signal having three carrier components. The three carrier components include a center carrier, a left carrier, and a right carrier. The center carrier, the left carrier, and the right carrier are separated by approximately 1.25 MHz. The rotator is a lookup table rotator that includes a mechanism for selectively rotating the multi-carrier-signal clockwise or counter clockwise and outputting the left carrier or the right carrier, respectively, in response thereto.

Abstract: A deskew buffer 410 arrangement in a CDMA receiver allows for accurate combining of symbols from a plurality of demodulator fingers, 402 and 404, without any symbol losses when the data rate is changed. A single deskew buffer 410 is coupled to a plurality of demodulator fingers, each of which demodulate an assigned multipath. The symbols are written into the deskew buffer 410 according to a PN count value modified by a predetermined bit pattern. The demodulator finger is able to demodulate a plurality of data rates corresponding to a plurality of Walsh lengths. Each data rate is assigned a corresponding deskew index. The PN count value represents an address within the deskew buffer 410. The lower bits of the PN count, where the number of bits corresponds to the deskew index, are truncated and replaced with the predetermined bit pattern. In one embodiment the predetermined bit pattern is all ones.

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

Abstract: Provided is a system and method for constructing a data message in a communications device including a processor configured to process sequentially transmitted messages. Each of the messages requires a predetermined number of data frames. The technique of the instant invention includes receiving portions of at least two of the transmitted messages in the processor. Each of the at least two received portions includes a subset of the predetermined number of data frames and excludes a remainder of the predetermined number of data frames. The subset of one of the received portions substantially matches the remainder of the other portion. Next, a determination is made as to whether a total number of the received subsets equals the predetermined number. Finally, a synthesized messaged is produced when the total number of the subsets is at least equal to the predetermined number. The synthesized message is formed of a combination of the subsets from each of the received portions.

Abstract: A bi-directional vector rotator that can be used to provide outputs having phases that are rotated in clockwise and counter clockwise directions relative to that of the input signal. The bi-directional vector rotator includes a product term generator that receives a complex input and a complex carrier signal and generates product terms. Combiners then selectively combine the product terms to generate the outputs. By sharing the same product term generator for both clockwise and counter clockwise phase rotations, the bi-directional vector rotator can be implemented using less circuitry than that for a conventional design employing two uni-directional vector rotators. Moreover, only one complex carrier signal is needed by the bi-directional vector rotator instead of two for the conventional design. Further simplification in the design of the bi-directional vector rotator can be achieved by selecting the proper sampling rate for the complex input.

Abstract: An efficient turbo decoder. The disclosed turbo decoder includes a first mode of operation in which the turbo decoder uses a first functional loop. The first functional loop includes a memory bank, a read interleaver, a first multiplexer (MUX), a RAM file, a log-MAP decoder, a write interleaver, and a second MUX. The disclosed turbo decoder further includes a second mode of operation in which a second functional loop is used. The second functional loop includes the memory bank, the first MUX, the RAM file, the log-MAP decoder, and the second MUX. The memory bank is a dual port extrinsic memory. The disclosed turbo decoder circuit switches between the first mode and the second mode.

Abstract: A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

Abstract: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.