Abstract: The disclosed method of operation for a data latch (DLATCH) circuit may include receiving, by an input component of the DLATCH circuit, an input signal. The method may additionally include storing, by a combinatorial gate of the DLATCH circuit, a state of the input signal, wherein the combinatorial gate corresponds to at least one of an AND-OR-inverted (AOI22) cell or an OR-AND-inverted (OAI22) cell. The method may further include providing an output signal, by an output component of the DLATCH circuit, wherein the output signal has the state stored by the combinatorial gate. Various other methods, systems, and circuits are also disclosed.

Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.

Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Abstract: In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.

Abstract: In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.

Abstract: In accordance with the teachings described herein, systems and methods are provided for reducing the lock time of a phase locked loop circuit. A phase comparator may be used to detect a phase error between an input reference signal and a feedback clock signal. A frequency synthesizer circuit may be used to control the frequency of an output clock signal as a function of the phase error between the input signal and the feedback clock signal. A feedback divider may be used to divide the frequency of the output clock signal to generate the feedback clock signal. A phase error monitor may be used to detect when the phase error between the input signal and the feedback clock signal reaches a peak value, and in response to detecting the peak value, initialize the feedback divider to reduce the phase error between the input signal and the feedback clock signal.

Abstract: In accordance with the teachings described herein, systems and methods are provided for reducing the lock time of a phase locked loop circuit. A phase comparator may be used to detect a phase error between an input reference signal and a feedback clock signal. A frequency synthesizer circuit may be used to control the frequency of an output clock signal as a function of the phase error between the input signal and the feedback clock signal. A feedback divider may be used to divide the frequency of the output clock signal to generate the feedback clock signal. A phase error monitor may be used to detect when the phase error between the input signal and the feedback clock signal reaches a peak value, and in response to detecting the peak value, initialize the feedback divider to reduce the phase error between the input signal and the feedback clock signal.