Patents by Inventor Ioan Domsa

Ioan Domsa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894240
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 6, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Patent number: 11837652
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: December 5, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Publication number: 20230304741
    Abstract: The disclosure describes equipment for magnetic annealing of a substrate, the equipment including: an anneal chamber configured to heat and cool a substrate held at a soak location along a first direction in the anneal chamber, the anneal chamber including: a heater, a cooler, and a substrate lifter including a substrate holder, where the substrate holder is configured to support a substrate oriented such that the first direction is perpendicular to a major surface of the substrate; and a magnet assembly configured to establish a homogeneous zone in the anneal chamber, the soak location being within the homogeneous zone, the homogeneous zone including a region of magnetic field.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Bartlomiej Burkowicz, Barry Clarke, David Hurley, Einstein Noel Abarra
  • Patent number: 11527345
    Abstract: An apparatus for magnetic annealing one or more workpieces, and a method of operating the apparatus, are described. The apparatus includes: a workpiece holder configured to support one or more workpieces, wherein the one or more workpieces having at least one substantially planar surface; an optional workpiece heating system configured to elevate the one or more workpieces to an anneal temperature; and a magnet assembly having a first magnet and a second magnet, the first and second magnets defining a gap between opposing poles of each magnet, wherein the magnet assembly is arranged to generate a magnetic field substantially perpendicular to the planar surface of the one or more workpieces.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 13, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Toru Ishii, Makoto Saito, David Hurley, Noel O'Shaughnessy, Barry Clarke, Gerhardus Van Der Linde, Pat Hughes
  • Patent number: 11521876
    Abstract: A horizontal substrate carrier is provided, for example a carrier for holding semiconductor substrates during horizontal thermal processing. The horizontal substrate carrier has asymmetrically placed support rails. One side of the horizontal substrate carrier has no upper rail while the other side of the horizontal substrate carrier has an upper rail placed at a relatively high location, for example at an angular location of 60° or more, more preferably of 70° or more, and most preferably at 90°. The side without an upper rail may be used for robotic loading of the horizontal substrate carrier. In a preferred embodiment, only three rails are provided: one upper rail on one side and two lower rails. The use and placement of these three rails can hold the substrate in precise uniform locations, minimize substrate movement, and minimize particle generation, all while allowing for easy robotic access.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 6, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Ioan Domsa, Ian Colgan, Makoto Saito, Mitsuru Yamazaki, George Eyres
  • Publication number: 20220262921
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: David Hurley, Ioan Domsa, lan Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Patent number: 11335792
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 17, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Publication number: 20210313444
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Publication number: 20210313189
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Application
    Filed: February 25, 2021
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Publication number: 20190371506
    Abstract: An apparatus for magnetic annealing one or more workpieces, and a method of operating the apparatus, are described. The apparatus includes: a workpiece holder configured to support one or more workpieces, wherein the one or more workpieces having at least one substantially planar surface; an optional workpiece heating system configured to elevate the one or more workpieces to an anneal temperature; and a magnet assembly having a first magnet and a second magnet, the first and second magnets defining a gap between opposing poles of each magnet, wherein the magnet assembly is arranged to generate a magnetic field substantially perpendicular to the planar surface of the one or more workpieces.
    Type: Application
    Filed: January 3, 2018
    Publication date: December 5, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Ian COLGAN, Ioan DOMSA, George EYRES, Toru ISHII, Makoto SAITO, David HURLEY, Noel O'SHAUGHNESSY, Barry CLARKE, Jattie VAN DER LINDE, Pat HUGHES
  • Patent number: 10473399
    Abstract: Disclosed is a connection structure that connects a housing to a magnetic annealing furnace that is provided with a fixedly arranged magnet and includes a first drum flange having a cylindrical flange portion. The connection structure includes: a second drum flange that is attached and fixed to the housing and includes a flange portion configured to externally or internally fit the flange portion of the first drum flange thereto; a first sealant that is installed between facing surfaces of the housing and the second drum flange; and a second sealant that is installed between facing surfaces of the first and second drum flanges.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: November 12, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Ian Colgan, George Eyres, Ioan Domsa, Junichi Sato, Koyu Hasegawa, Tomoaki Abe
  • Publication number: 20190279891
    Abstract: A horizontal substrate carrier is provided, for example a carrier for holding semiconductor substrates during horizontal thermal processing. The horizontal substrate carrier has asymmetrically placed support rails. One side of the horizontal substrate carrier has no upper rail while the other side of the horizontal substrate carrier has an upper rail placed at a relatively high location, for example at an angular location of 60° or more, more preferably of 70° or more, and most preferably at 90°. The side without an upper rail may be used for robotic loading of the horizontal substrate carrier. In a preferred embodiment, only three rails are provided: one upper rail on one side and two lower rails. The use and placement of these three rails can hold the substrate in precise uniform locations, minimize substrate movement, and minimize particle generation, all while allowing for easy robotic access.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 12, 2019
    Inventors: Ioan Domsa, Ian Colgan, Makoto Saito
  • Patent number: 10254046
    Abstract: Disclosed is a magnetic annealing apparatus including a processing container having a horizontally-elongated tubular shape and configured to perform a magnetic annealing processing on a plurality of substrates accommodated therein in a magnetic field; a heating unit provided to cover at least a part of a surface of the processing container that extends in a longitudinal direction, from outside; a magnet provided to cover the heating unit from the outside of the heating unit; a substrate holder configured to hold the plurality of substrates within the processing container; and a heat shielding plate provided to surround a part of the substrate holder.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: April 9, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuru Yamazaki, Barry Clarke, Ian Colgan, George Eyres, Ioan Domsa
  • Patent number: 10003018
    Abstract: Embodiments are described for annealing systems and related methods to process microelectronic workpieces using vertical multi-batch perpendicular magnetic annealing systems that allow for a side-by-side configuration of multiple annealing systems to satisfy reduced footprint requirements.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 19, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Saito Makoto, Noel O'Shaughnessy, Toru Ishii, David Hurley
  • Patent number: 9410742
    Abstract: An annealing system and method of operating is described. The annealing system includes a vertical furnace having an inner cylindrical insulating tube and at least one heating element surrounding an outer surface thereof, wherein the inner cylindrical insulating tube defines a processing space into which a plurality of workpieces may be vertically translated and subjected to thermal and/or magnetic processing. The annealing system further includes a workpiece boat for carrying at least one hundred workpieces, a boat loader arranged beneath the vertical furnace, and configured to vertically translate the workpiece boat and position the workpieces within the processing space, and a magnet system arranged outside the vertical furnace and configured to generate a magnetic field within the processing space.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 9, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Toru Ishii
  • Publication number: 20160216032
    Abstract: Disclosed is a connection structure that connects a housing to a magnetic annealing furnace that is provided with a fixedly arranged magnet and includes a first drum flange having a cylindrical flange portion. The connection structure includes: a second drum flange that is attached and fixed to the housing and includes a flange portion configured to externally or internally fit the flange portion of the first drum flange thereto; a first sealant that is installed between facing surfaces of the housing and the second drum flange; and a second sealant that is installed between facing surfaces of the first and second drum flanges.
    Type: Application
    Filed: January 20, 2016
    Publication date: July 28, 2016
    Inventors: Ian Colgan, George Eyres, Ioan Domsa, Junichi Sato, Koyu Hasegawa, Tomoaki Abe
  • Publication number: 20160069613
    Abstract: An annealing system and method of operating is described. The annealing system includes a vertical furnace having an inner cylindrical insulating tube and at least one heating element surrounding an outer surface thereof, wherein the inner cylindrical insulating tube defines a processing space into which a plurality of workpieces may be vertically translated and subjected to thermal and/or magnetic processing. The annealing system further includes a workpiece boat for carrying at least one hundred workpieces, a boat loader arranged beneath the vertical furnace, and configured to vertically translate the workpiece boat and position the workpieces within the processing space, and a magnet system arranged outside the vertical furnace and configured to generate a magnetic field within the processing space.
    Type: Application
    Filed: June 26, 2015
    Publication date: March 10, 2016
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Toru Ishii
  • Publication number: 20160061526
    Abstract: Disclosed is a magnetic annealing apparatus including a processing container having a horizontally-elongated tubular shape and configured to perform a magnetic annealing processing on a plurality of substrates accommodated therein in a magnetic field; a heating unit provided to cover at least a part of a surface of the processing container that extends in a longitudinal direction, from outside; a magnet provided to cover the heating unit from the outside of the heating unit; a substrate holder configured to hold the plurality of substrates within the processing container; and a heat shielding plate provided to surround a part of the substrate holder.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 3, 2016
    Inventors: Mitsuru Yamazaki, Barry Clarke, Ian Colgan, George Eyres, Ioan Domsa