Abstract: A system for providing a feedback signal in a telecommunications network is provided that includes a plurality of bus control modules, a lower level distribution module, and a timing generator. The bus control modules are operable to generate a feedback signal. The lower level distribution module is coupled to the bus control modules. The lower level distribution module is operable to receive the feedback signal and to insert feedback information for the lower level distribution module into the feedback signal. The timing generator is coupled to the lower level distribution module. The timing generator is operable to receive the feedback signal and to provide the feedback signal to a controller for response.

Abstract: A system for distributing a timing signal is disclosed. A timing generator inserts a phase of a timing signal and a command signal into a framed signal. A distribution module receives the framed signal from the timing generator. A bus control module receives the framed signal from the distribution module and distributes the framed signal to a telecommunication system. A method for distributing a timing signal in a telecommunication system is disclosed. A phase of a timing signal and a command signal is inserted into a framed signal using a timing generator. The framed signal is transmitted to a distribution module. The framed signal is transmitted to a bus control module. The framed signal is distributed to a telecommunication system using the bus control module.

Abstract: A system for distributing a synchronization signal in a telecommunications network is provided that includes a timing generator, a lower level distribution module, a bus control module and a plurality of cards. The timing generator is operable to provide a synchronization signal comprising timing and control signals. The lower level distribution module is coupled to the timing generator. The lower level distribution module is operable to receive and distribute the synchronization signal. The bus control module is coupled to the lower level distribution module. The bus control module is operable to receive and distribute the synchronization signal. The plurality of cards are coupled to the bus control module. Each card is operable to receive the synchronization signal and to synchronize based on the timing signals.

Abstract: A system for generating a timing signal is disclosed. A processor generates a selection command. A clock receives a signal selected in response to the selection command and converts the selected signal to a timing signal. A framing module inserts a phase of the timing signal into a framed signal. A method for generating a timing signal for a telecommunication system is disclosed. A selection command is generated using a processor. A signal is selected in response to the selection command. The selected signal is converted to a timing signal using a clock. A phase of the timing signal is inserted into a framed signal using a framing module.

Abstract: A method for determining the change in frequency of a clock signal (168). The method includes the step of counting the number of clock signal cycles (168) that occur over at least two time windows (162, 164). The number of clock signal cycles counted in the first time window (162) is compared to the number of clock signal cycles counted in the second time window (164).

Abstract: A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18).

Abstract: In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry (8, 100) for aligning first and second redundant timing signals (10, 12, 110, 112) and switching therebetween. The circuitry includes first and second phase-locked loops (18, 20, 118, 120) for receiving first and second redundant timing signals (10, 12, 110, 112), respectively, and multiplying the frequency of first and second redundant timing signals (10, 12, 110, 112) by a factor of N. The circuitry further includes a selecting and switching circuitry (34, 134) for receiving the multiplied first and second redundant timing signals (22, 23, 122, 124) and designating one as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal (54, 154).

Abstract: A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18).

Abstract: An integrated data voice multiplexer (IDVM) capable of simultaneously supporting loop-back and communication handshake protocols with no performance degradation. This allows the IDVM to be used in both point-to-point and packet switch networks. The IDVM is of the type using frequency shift keyed FSK modulation of two or more carriers to send a data signal. The presence or absence of carrier signals indicates loop-back state. Narrowband modulation is selectively added to at least one carrier to support handshake protocol. The preferred narrowband modulation is biphase at a rate lower than the FSK modulation rate. Encoder, decoder, data hold and detect circuits for supporting standard RS232 protocol are disclosed.