Abstract: Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (OPC). Methods according to the disclosure can include: fabricating a circuit using a proposed IC layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (SRAF) from the proposed IC layout; determining the predicting as being correct when the fabricated circuit includes the printed SRAF, or as being incorrect when the fabricated circuit does not include the printed SRAF; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule waiver system. The design rule waiver system may process the first design rule to extract a plurality of descriptors that can be perturbed. The design rule waiver system may perturb an attribute associated with at least one of the plurality of descriptors extracted from the first design rule in order to define a second design rule that is satisfied by the plurality of patterns.

Abstract: Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (OPC). Methods according to the disclosure can include: fabricating a circuit using a proposed IC layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (SRAF) from the proposed IC layout; determining the predicting as being correct when the fabricated circuit includes the printed SRAF, or as being incorrect when the fabricated circuit does not include the printed SRAF; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule waiver system. The design rule waiver system may process the first design rule to extract a plurality of descriptors that can be perturbed. The design rule waiver system may perturb an attribute associated with at least one of the plurality of descriptors extracted from the first design rule in order to define a second design rule that is satisfied by the plurality of patterns.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

Abstract: Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

Abstract: A method for designing alternating phase shift masks is provided, in which narrow phase shapes located between densely spaced design shapes are colored to allow a maximum amount of light transmission. After assigning and ensuring binary legalization of the phase shapes, the narrow phase shapes are assigned a color, such as 0° phase shift, that allows the more light transmission than the alternate or opposite color (e.g. 180° phase shift), which helps avoid printing errors such as resist scumming between closely spaced shapes, and maximizes the lithographic process window.

Abstract: A method for increasing coverage of subresolution assist features (SRAFs) in a layout. A set of possible SRAF placement and sizing rules for a given pitch is provided, ranked according to some figure of merit. During SRAF placement, the fit of a plurality of different SRAF solutions is successively evaluated to find the SRAF solution, or combinations thereof, which most improves lithographic performance while avoiding manufacturability problems. In general, the method comprises: obtaining a plurality of SRAF configurations for the layout; ranking the SRAF configurations based on a figure of merit; applying a highest ranked SRAF configuration to the layout; applying a predetermined number of lower ranked SRAF configurations to the layout; and selecting SRAF features from at least one of the applied SRAF configurations to provide the optimal SRAF configuration for the layout.

Abstract: A method for model-based verification of resolution enhancement techniques (RET) and optical proximity correction (OPC) in lithography includes scaling shapes of a drawn mask layout to their corresponding intended wafer dimensions so as to create a scaled image. A first feature of the scaled image is shifted with respect to a second feature thereof in accordance with a predetermined maximum overlay error. An intersection parameter of the first and said second features of the scaled image is calculated so as to determine a yield metric of an ideal layout. A first feature of a simulated wafer image is shifted with respect to a second feature thereof in accordance with the predetermined maximum overlay error. An intersection parameter of the first and said second features of the simulated wafer image is calculated so as to determine a yield metric of a simulated layout, and the yield metric of the simulated wafer image is compared to the yield metric of the scaled image.

Abstract: A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.

Abstract: A computer-implemented routine that verifies that an existing chip design can be converted to a PSM or reports localized design conflicts based solely on a knowledge of the specific design constraints applied in the targeted PSM design system and without a prior knowledge of specific layout configurations that will cause PSM design errors.