Abstract: Systems and techniques are described for generating depth map(s). For Depth Imaging System instance, a process can include obtaining a frame including a reflected pattern of light generated based on a pattern of light that is based on a primitive including a set of flight (ToF) sensor, a first distance measurement associated with a pixel of the frame, and determining a search space within the primitive based on the first distance measurement. The process can include determining, based on searching the search space, a feature of the primitive corresponding to a region around the pixel of the frame. The process can include determining a second distance measurement associated with the pixel of the frame based on determining the feature of the primitive. The process can include generating a depth map based at least in part on the second distance measurement.

Abstract: Aspects of the disclosure relate to decoding an image for active depth sensing. An example method includes receiving an image. The image includes one or more reflections of a distribution of light. The method also includes sampling a first region of the image using a first sampling grid to generate a first image sample, sampling a second region of the image using a second sampling grid different from the first sampling grid to generate a second image sample, determining a first depth value based on the first image sample, and determining a second depth value based on the second image sample.

Abstract: Aspects of the present disclosure relate to systems and methods for active depth sensing. An example apparatus configured to perform active depth sensing includes a projector. The projector is configured to emit a first distribution of light during a first time and emit a second distribution of light different from the first distribution of light during a second time. A set of final depth values of one or more objects in a scene is based on one or more reflections of the first distribution of light and one or more reflections of the second distribution of light. The projector may include a laser array, and the apparatus may be configured to switch between a first plurality of lasers of the laser array to emit light during the first time and a second plurality of laser to emit light during the second time.

Abstract: Aspects of the present disclosure relate to systems and methods for active depth sensing. An example apparatus configured to perform active depth sensing includes a projector. The projector is configured to emit a first distribution of light during a first time and emit a second distribution of light different from the first distribution of light during a second time. A set of final depth values of one or more objects in a scene is based on one or more reflections of the first distribution of light and one or more reflections of the second distribution of light. The projector may include a laser array, and the apparatus may be configured to switch between a first plurality of lasers of the laser array to emit light during the first time and a second plurality of laser to emit light during the second time.

Abstract: According to various aspects, a sorting instruction described herein may advantageously be implemented using intrinsic properties of a reconfigurable computing engine. For example, the reconfigurable computing engine may comprise an arithmetic logic unit (ALU) or other suitable operational unit(s) that can perform one or more comparisons among a given plurality of inputs and output a plurality of select signals that at least indicate maximum and minimum values among the given plurality of inputs. In addition, the reconfigurable computing engine may comprise various multiplexers that make up an interconnect fabric coupled to the ALU or other suitable operational units, wherein the multiplexers may be arranged to receive the plurality of inputs and the plurality of select signals such that the plurality of multiplexers can be dynamically configured to perform the permutations to sort the plurality of inputs.

Abstract: A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

Abstract: A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

Abstract: A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfacesand an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations isknown before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate timeswrite-enable inputs of configuration registers are disabled.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract: An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals.

Abstract: An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words.

Abstract: A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract: An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses.

Abstract: A reconfigurable processor architecture, compiler and method of program instruction execution provides reduced cost, short design time, low power consumption and high performance. The processor executes program instructions having datapaths of both dependent and independent program instructions. Simultaneous multithreading is also Interconnects Network supported. The processor has a reconfigurable core (1) with an interconnection network (4) and a heterogeneous array of instruction cells (2) each connected to the interconnection network (4). A decoding module (11) receives configuration instruction (10), each instruction encoding the mapping of one of the datapaths to a circuit of the instruction cells (2). The decoding module (11) decodes each configuration instruction (10) and configures the interconnection network (4) and instruction cells in order to map the datapath to the circuit of the instruction cells and execute the program instructions.