Abstract: A physical layer based technique secures wireless communication between a transmitter and receiver. The technique involves obfuscating the preamble data of the baseband signal through unique keys that are generated at the transmitter and the receiver based on channel characteristics known only to them.

Abstract: A key-based interleaver for enhancement the security of wireless communication includes a physical layer communication channel key to provide security even when the software encryption key is compromised. A method of creating a secure communication link using a physical layer interleaving system includes implementing a key policy implementation that utilizes temporal dependency and interleaving bits using a flexible inter and intra-block data interleaver.

Abstract: There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. Each of these may encrypt a circuit with certain advantages in delay and power consumption.

Abstract: A real-time workload scheduling heuristic assigns tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators.

Abstract: A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor (width and length) and the circuit parameters reliant upon these physical characteristics (i.e. circuit biasing conditions, phase noise profile, bandwidth, gain, noise figure, operating frequency, etc.). The proposed key based obfuscation technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The widths and/or lengths of a transistor are obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied and certain transistor(s) are active, are the correct biasing conditions at the target node set.

Abstract: A circuit that detects the power supply voltage requirement of each voltage domain in an IC includes 1) a ring oscillator in each voltage domain, and 2) a power module. Two different circuit implementations of the power module may provide a precise reference voltage to on-chip voltage regulators (LDO or DC-DC switching buck converter). The power module supports DVFS and can provide the desired power supply voltage for advanced CMOS technology nodes (45 nm and beyond) in less than 100 ns. The voltage detection circuit clamps the voltage to the desired level to address power supply voltage variations due to PVT and ageing. The proposed technique has minimal power and area overhead to compensate for the power supply voltage variation, thus reducing power supply voltage margins which yields higher power saving.

Abstract: A circuit that detects the power supply voltage requirement of each voltage domain in an IC includes 1) a ring oscillator in each voltage domain, and 2) a power module. Two different circuit implementations of the power module may provide a precise reference voltage to on-chip voltage regulators (LDO or DC-DC switching buck converter). The power module supports DVFS and can provide the desired power supply voltage for advanced CMOS technology nodes (45 nm and beyond) in less than 100 ns. The voltage detection circuit clamps the voltage to the desired level to address power supply voltage variations due to PVT and ageing. The proposed technique has minimal power and area overhead to compensate for the power supply voltage variation, thus reducing power supply voltage margins which yields higher power saving.