Abstract: The present invention is directed toward identifying selected values from among a set of values. In accordance with an embodiment, a method of identifying two selected values from among a plurality of values comprises: partitioning the plurality of values into pairs of values; for each pair of values, using a comparator to select one of the two values to form a vector from the selected value of each pair; and applying the vector to a hardware unit that identifies first and second extreme values from among the values of the vector.

Abstract: An improved LDPC encoding and encoding and associated architectures therefor are described. In one exemplary embodiment, a set of parity bits (p) are generated from a set of information bits (s), by storing information related to z×z sub-matrices of a first sub-matrix and of a second sub-matrix corresponding to a first and a second portion of a parity check matrix H of an LDPC code, to allow representation of the parity check matrix in a compressed form and by generating the set of parity bits p by appropriately multiplying, shifting and accumulating subsets from the set of information bits s based on the stored information, without decompressing the parity check matrix. Further relevant techniques are also described.

Abstract: The present invention is directed toward reconfigurable barrel shifters and rotators. A barrel shifter comprises an array of multiplexers, the array having a plurality of inputs and a plurality of outputs and wherein the array of multiplexers is configured to rotate a set of n input messages applied to the inputs by a selected number of positions at the outputs and wherein the number n of messages contained in the set is selectable from among a plurality of values, by changing only select control signal inputs to the array of multiplexers.

Abstract: The present disclosure relates to techniques used for improved LDPC encoding and encoding and associated architectures therefor. In one exemplary embodiment, a set of parity bits (p) are generated from a set of information bits (s), by storing information related to z×z sub-matrices of a first sub-matrix and of a second sub-matrix corresponding to a first and a second portion of a parity check matrix H of an LDPC code, to allow representation of the parity check matrix in a compressed form and by generating the set of parity bits p by appropriately multiplying, shifting and accumulating subsets from the set of information bits s based on the stored information, without decompressing the parity check matrix. Further relevenat techniques are also described.