Patents by Inventor Ioulia Smorchkova
Ioulia Smorchkova has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9196703Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.Type: GrantFiled: August 20, 2014Date of Patent: November 24, 2015Assignees: Northrop Grumman Systems Corporation, The United States of America, as Represented by the Secretary of the Navy, The Regents of the University of CaliforniaInventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene I. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Rajinder S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
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Patent number: 9048184Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.Type: GrantFiled: March 15, 2013Date of Patent: June 2, 2015Assignee: Northrop Grumman Systems CorporationInventors: Carol O. Namba, Po-Hsin Liu, Sumiko Poust, Ioulia Smorchkova, Michael Wojtowicz, Ronald Grundbacher
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Publication number: 20150056763Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.Type: ApplicationFiled: August 20, 2014Publication date: February 26, 2015Inventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene A. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Randijer S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
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Publication number: 20140264448Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Northrop Grumman Systems CorporationInventors: CAROL O. NAMBA, Po-Hsin Lin, Poust Sumiko, Ioulia Smorchkova, Michael Wojtowicz, Ronald Grundbacher
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Patent number: 8431962Abstract: A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.Type: GrantFiled: December 7, 2007Date of Patent: April 30, 2013Assignee: Northrop Grumman Systems CorporationInventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
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Patent number: 7897446Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: GrantFiled: March 25, 2010Date of Patent: March 1, 2011Assignee: Northrop Grumman Systems CorporationInventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7800766Abstract: A method and apparatus 10 for detecting the height of non-flat and transparent substrates using one or more reflectors 30 patterned on the surface of the substrate 40 and adjusting the position of the substrate in its holder based on measurement of the height of the reflectors in comparison to a calibration marker 60 on the holder and using appropriate spacers 50 with appropriate thickness to adjust the placement of the substrate at various locations to place the greatest portion of the substrate in an optimal focal range of the lithography system.Type: GrantFiled: September 21, 2007Date of Patent: September 21, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Mike Wojtowicz, Rob Coffie
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Patent number: 7800132Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.Type: GrantFiled: October 25, 2007Date of Patent: September 21, 2010Assignee: Northrop Grumman Systems CorporationInventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai
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Publication number: 20100184262Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: ApplicationFiled: March 25, 2010Publication date: July 22, 2010Applicant: Northrop Grumman Space and Mission Systems Corp.Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7750370Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: GrantFiled: December 20, 2007Date of Patent: July 6, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7632726Abstract: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.Type: GrantFiled: December 7, 2007Date of Patent: December 15, 2009Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
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Publication number: 20090267115Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
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Patent number: 7608865Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: GrantFiled: April 28, 2008Date of Patent: October 27, 2009Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
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Publication number: 20090146224Abstract: A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.Type: ApplicationFiled: December 7, 2007Publication date: June 11, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
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Publication number: 20090148985Abstract: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.Type: ApplicationFiled: December 7, 2007Publication date: June 11, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
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Publication number: 20090108299Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Applicant: Northrop Grumman Space and Mission Systems Corp.Inventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai
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Publication number: 20090078888Abstract: A method and apparatus 10 for detecting the height of non-flat and transparent substrates using one or more reflectors 30 patterned on the surface of the substrate 40 and adjusting the position of the substrate in its holder based on measurement of the height of the reflectors in comparison to a calibration marker 60 on the holder and using appropriate spacers 50 with appropriate thickness to adjust the placement of the substrate at various locations to place the greatest portion of the substrate in an optimal focal range of the lithography system.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Mike Wojtowicz, Rob Coffie
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Publication number: 20080199993Abstract: An improved method for fabricating an HEMT device having active device layers deposited on a semiconductor substrate. In an embodiment, the improved method comprises the steps of depositing an AlN layer over the active device layers using a relatively low temperature vacuum process to form an amorphous layer protecting the active device layers from unnecessary exposure to fabrication processes, and selectively forming openings in the AlN layer to expose portions of the active device layers for imminent process steps.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie