Patents by Inventor Iouri G. Smirnov

Iouri G. Smirnov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor-level layout synthesis
    Patent number: 8726218
    Abstract: A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert L. Maziasz, Vladimir P. Rozenfeld, Iouri G. Smirnov, Alexander V. Zhuravlev
  • TRANSISTOR-LEVEL LAYOUT SYNTHESIS
    Publication number: 20120159412
    Abstract: A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 21, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Robert L. Maziasz, Vladimir P. Rozenfeld, Iouri G. Smirnov, Alexander V. Zhuravlev