Abstract: A VCSEL array includes a base substrate, a plurality of VCSEL devices and an inter-device line. Each of the plurality of VCSEL devices is disposed on a front side of the base substrate. The inter-device line connects two of the plurality of VCSEL devices that are adjacent to each other, the two VCSEL devices being connected in series such that forward directions of the two VCSEL devices are the same. An insulating groove that electrically insulates the two VCSEL devices is formed on the base substrate.

Abstract: A cathode electrode, cathode pad electrodes, cathode wiring electrodes, an anode electrode, an anode pad electrode, and an anode wiring electrode are disposed on the surface of a vertical-cavity surface-emitting laser device. A light-emitting-region multilayer portion having active layers sandwiched by clad layers and DBR layers is formed directly below the anode electrode. A region where the light-emitting-region multilayer portion is formed serves as a light-emitting region. The light-emitting region is positioned closer to one end of the first direction than is a suction region onto which a flat collet sucks with respect to the first direction, in such a way that the light-emitting region is substantially in contact with or spaced a predetermined distance from the suction region.

Abstract: A VCSEL array includes a base substrate, VCSEL element columns arranged in a row direction (y direction) on a front-surface side of the base substrate and parallel wiring lines that connect the VCSEL element columns in parallel with each other. Each of the VCSEL element columns includes a plurality of VCSEL elements arranged in a column direction (x direction) and a plurality of series wiring lines. The plurality of series wiring lines serially connect every two VCSEL elements that are adjacent to each other in the column direction among the plurality of VCSEL elements in such an orientation that the forward directions of the two VCSEL elements match. Insulating grooves are formed on the base substrate. The insulating grooves electrically insulate the VCSEL element columns from each other. The insulating grooves electrically insulate the VCSEL elements from each other.

Abstract: A VCSEL array includes a base substrate, a plurality of VCSEL devices and an inter-device line. Each of the plurality of VCSEL devices is disposed on a front side of the base substrate. The inter-device line connects two of the plurality of VCSEL devices that are adjacent to each other, the two VCSEL devices being connected in series such that forward directions of the two VCSEL devices are the same. An insulating groove that electrically insulates the two VCSEL devices is formed on the base substrate.

Abstract: A VCSEL array includes a base substrate, VCSEL element columns arranged in a row direction (y direction) on a front-surface side of the base substrate and parallel wiring lines that connect the VCSEL element columns in parallel with each other. Each of the VCSEL element columns includes a plurality of VCSEL elements arranged in a column direction (x direction) and a plurality of series wiring lines. The plurality of series wiring lines serially connect every two VCSEL elements that are adjacent to each other in the column direction among the plurality of VCSEL elements in such an orientation that the forward directions of the two VCSEL elements match. Insulating grooves are formed on the base substrate. The insulating grooves electrically insulate the VCSEL element columns from each other. The insulating grooves electrically insulate the VCSEL elements from each other.

Abstract: Provided are a base substrate made of a semi-insulating semiconductor; an emission region multilayer unit formed on a surface of the base substrate and including each of an N-type semiconductor contact layer, an N-type DBR layer, an active layer, a P-type semiconductor DBR layer, and a P-type semiconductor contact layer; an anode electrode connected to the P-type semiconductor contact layer; and a cathode electrode formed on a surface side of the base substrate and connected to the N-type semiconductor contact layer. The N-type DBR layer is formed of 15 or more pairs of layers with different compositions laminated on each other. Through this configuration, a vertical-cavity surface-emitting laser that can suppress an occurrence of a defect caused by crystal missing arising from the base substrate can be provided at reduced cost.

Abstract: A vertical cavity surface emitting laser includes an active layer that includes a quantum well, a first cladding layer and a second cladding layer between which the active layer is interposed. A first multilayer reflector layer is arranged on a side of the first cladding layer opposite to that on which the active layer is arranged. A second multilayer reflector layer is arranged on a side of the second cladding layer opposite to that on which the active layer is arranged. At least one of the first cladding layer and the second cladding layer includes a low activity energy layer having a band gap that is smaller than a smallest band gap of an optical confinement layer for forming the quantum well of the active layer and larger than a band gap of the quantum well.

Abstract: A vertical cavity surface emitting laser includes a base substrate formed by a semi-insulating semiconductor, a light-emitting region multilayer portion including an N-type semiconductor contact layer, an N-type semiconductor multilayer-film reflecting layer, an N-type semiconductor clad layer, an active layer provided with a quantum well, a P-type semiconductor clad layer, a P-type semiconductor multilayer-film reflecting layer, and a P-type semiconductor contact layer, which are formed on the surface of the base substrate sequentially, an anode electrode formed on the surface of the P-type semiconductor contact layer, and a cathode electrode that is connected to the N-type semiconductor clad layer. The cathode electrode is formed on the base substrate at the side of the light-emitting region multilayer portion. A groove is formed among respective vertical cavity surface emitting lasers.

Abstract: A cathode electrode, cathode pad electrodes, cathode wiring electrodes, an anode electrode, an anode pad electrode, and an anode wiring electrode are disposed on the surface of a vertical-cavity surface-emitting laser device. A light-emitting-region multilayer portion having active layers sandwiched by clad layers and DBR layers is formed directly below the anode electrode. A region where the light-emitting-region multilayer portion is formed serves as a light-emitting region. The light-emitting region is positioned closer to one end of the first direction than is a suction region onto which a flat collet sucks with respect to the first direction, in such a way that the light-emitting region is substantially in contact with or spaced a predetermined distance from the suction region.

Abstract: A vertical cavity surface emitting laser includes an active layer that includes a quantum well, a first cladding layer and a second cladding layer between which the active layer is interposed. A first multilayer reflector layer is arranged on a side of the first cladding layer opposite to that on which the active layer is arranged. A second multilayer reflector layer is arranged on a side of the second cladding layer opposite to that on which the active layer is arranged. At least one of the first cladding layer and the second cladding layer includes a low activity energy layer having a band gap that is smaller than a smallest band gap of an optical confinement layer for forming the quantum well of the active layer and larger than a band gap of the quantum well.