Patents by Inventor Ippei Nodo

Ippei Nodo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8102156
    Abstract: A differential amplifier circuit comprises a first input transistor including a control electrode serving as a non-inversion input terminal and a second input transistor including a control electrode serving as an inversion input terminal. These first and second input transistors constitute a difference pair. A bias current generation circuit section is provided to generate a bias current flowing to the first and second input transistors. An offset adjustment circuit section is provided to adjust an input offset voltage appearing at these input terminals. The offset adjustment circuit section has an adjustment resistance formed from a first variable resistance inserted into a first current route connecting to the first input transistor and a second variable resistance inserted into a second current route connecting to the second input transistor. The bias current generation circuit section changes the bias current in accordance with a change in a value of the adjustment resistance.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: January 24, 2012
    Assignee: Ricoh Company, Ltd.
    Inventor: Ippei Nodo
  • Publication number: 20080061745
    Abstract: A differential amplifier circuit comprises a first input transistor including a control electrode serving as a non-inversion input terminal and a second input transistor including a control electrode serving as an inversion input terminal. These first and second input transistors constitute a difference pair. A bias current generation circuit section is provided to generate a bias current flowing to the first and second input transistors. An offset adjustment circuit section is provided to adjust an input offset voltage appearing at these input terminals. The offset adjustment circuit section has an adjustment resistance formed from a first variable resistance inserted into a first current route connecting to the first input transistor and a second variable resistance inserted into a second current route connecting to the second input transistor. The bias current generation circuit section changes the bias current in accordance with a change in a value of the adjustment resistance.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 13, 2008
    Inventor: Ippei Nodo