Patents by Inventor Ippei Yasuda
Ippei Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074170Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers arranged along a vertical direction, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer. The blocking dielectric film includes component layers which include, from a side that is proximal to the vertical stack of memory elements toward a side that is distal from the vertical stack of memory elements, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Takashi YUDA, Noriyuki NAGAHATA, Ippei YASUDA
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Publication number: 20220052073Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of in-process composite layers and sacrificial material layers including a lower insulating layer, a sacrificial spacer layer including silicon nitride or a semiconductor material, and an upper insulating layer, forming a memory opening vertically extending through the vertical stack, forming a memory opening fill structure in the memory opening, the memory opening fill structure including an in-process memory film and a vertical semiconductor channel, forming backside trenches through the alternating stack, replacing the sacrificial material layers with electrically conductive layers by removing the sacrificial material layers to form backside recesses and by depositing an electrically conductive material in the backside recesses, and converting the in-process composite layers into composite insulating layers by removing the sacrificial spacer layers to form lateral cavities and by optionally depositing replacement diType: ApplicationFiled: October 27, 2021Publication date: February 17, 2022Inventors: Keigo KITAZAWA, Ippei YASUDA, Adarsh RAJASHEKHAR
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Patent number: 11227663Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: February 10, 2021Date of Patent: January 18, 2022Assignee: SanDisk Technologies LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Patent number: 11114462Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.Type: GrantFiled: February 19, 2020Date of Patent: September 7, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Ippei Yasuda
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Publication number: 20210257379Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Inventors: Zhixin CUI, Ippei YASUDA
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Publication number: 20210174881Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: February 10, 2021Publication date: June 10, 2021Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Patent number: 10957401Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 23, 2020Date of Patent: March 23, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Patent number: 10950311Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 28, 2019Date of Patent: March 16, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Publication number: 20200411112Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Publication number: 20200411115Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: June 23, 2020Publication date: December 31, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani