Abstract: A multiple-input, mixed-type bar code processor, comprising: a plurality of retriggerable pulse generators, each having data inputs coupled to sources of potential representing fixed logic levels and each having at least one of a clear and a reset input coupled to a different one of a plurality of sources of input bar code data streams, for regenerating the input bar code data streams responsive to logic level transitions of the input bar code data streams, both when any input bar code data stream is logically low absent scanned data and when any other input bar code data stream is logically high absent the scanned data; a circuit for receiving all of the regenerated bar code data streams and generating a single output bar code data stream; and, a bar code data stream decoder coupled for receiving the single output bar code data stream.

Abstract: An improved frequency and phase lock detection circuit includes a first circuit for receiving a first signal and a second circuit for receiving a second signal. A detecting circuit detects that one of the first and second signals is being received by one of the first and second receiving circuits and produces a detect signal indicative thereof. A comparing circuit detects that the first and second signals have substantially the same frequency and phase and produces a compare signal indicative thereof. An output circuit receives the detect signal and the compare signal and produces a locked signal in response thereto which indicates that at least one of the first and second signals is being received and that the first and second signals are substantially identical in frequency and phase.