Abstract: In one embodiment, a fan out buffer has the inputs of a plurality of output followers connected to the output of a plurality of distribution gates.

Abstract: In one embodiment, a delay circuit is formed to use cascode coupled transistors to receive signals from a differential pair and increase the propagation through the delay circuit.

Abstract: In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die.

Abstract: In one embodiment, a pair of differential amplifiers have outputs coupled together. A signal received on one input results in signals coupled to the outputs that substantially cancel each other at the outputs.

Abstract: In one embodiment, an ECL logic device uses a capacitor to couple a positive voltage to an output and reduce the rise time of the output signal.

Abstract: In one embodiment, a differential amplifier uses a diode coupled transistor and a series resistor to set a Voh output level and uses another transistor in parallel with the diode coupled transistor and resistor to set a Vol output level.

Abstract: A reference voltage generator (10) is formed to include a bipolar current mirror the forms an output current (24) that is a function of a Vbe voltage of a reference transistor (14) and the difference between the Vbe voltage of the reference transistor (14) and a difference transistor (19).

Abstract: A reference voltage generator (10) is formed to include a bipolar current mirror the forms an output current (24) that is a function of a Vbe voltage of a reference transistor (14) and the difference between the Vbe voltage of the reference transistor (14) and a difference transistor (19).

Abstract: A circuit and method for correcting a sense signal of a sensor (100) where the sense signal is reduced by a negative nonlinear error component introduced by membrane stress in a sensor structure (101). A first transducer (103) is disposed at a location (203) having substantial bending stress to produce a sense signal having a linear component and the nonlinear error component. A second transducer (102) is disposed at a location (202) with substantially zero bending stress to produce a sense signal having the nonlinear error component but a substantially zero linear component. The sense signal from the second transducer (102) is added to the sense signal from the first transducer (103) to correct the nonlinear error for producing a linear output sense signal (VOUT) of the sensor (100) which is representative of the physical condition.

Abstract: A piezoresistive pressure sensor (30) has four resistive diffused regions (32) coupled into a bridge configuration (33) with four junctions (36) and four inside corners (40). Each of the diffused regions has a first end connected to one of the four junctions and a second end connected to a different one of the four junctions. There are four contact diffusion terminals (34) disposed in contact with the bridge configuration, and each of the diffusion terminals is disposed at one of the four junctions such that the diffused regions are electrically connected essentially only by the contact diffusion terminals and an overlap (44, 46) is provided between each of the diffusion terminals and the inside corners to accommodate mask misalignment during manufacture. Thus, no tap is required to electrically connect the contact diffusion terminals to the resistive diffused regions of the bridge, which results in increased sensor sensitivity.

Abstract: A compensation circuit (106) corrects for nonlinearities in a sensor signal representing the physical state of a sensor (100). A transducer (102) produces a non-linear component in a transducer voltage signal. A voltage-current converter (104) converts the tranducer voltage signal to a transducer current which contains the non-linear component. A compensation circuit (106) squares the transducer current (I.sub.216) and uses a scaling current (I.sub.412) to generate a compensation current (I.sub.408) equal to the non-linear component. The current (I.sub.216) and scaled compensation current (I.sub.408) are summed at a summing junction (418) to produce an output current (I.sub.OUT) which is a substantially linear representation of the physical state of the sensor.

Abstract: An edge die bond semiconductor package including a semiconductor die having an active major surface and a mounting edge substantially orthogonal to the active surface, a base having a mounting surface, and material affixing the mounting edge of the semiconductor die to the mounting surface of the base.

Abstract: A method for setting the sensing polarity of a sensor device (10) uses a switching bridge (22) having a wheatstone bridge configuration that is coupled to a sensing element (20) such that the polarity of the sensor device can be set by creating two electrical opens, for example with laser trimming along a cut line (59, 66), in parallel branches (30, 31) of the switching bridge. These opens are formed after the sensor device has been fully processed.

Abstract: A method of etching a semiconductor wafer includes providing a wafer having a portion thereof to be etched. A highly doped region is formed in the periphery of the wafer which is subsequently etched. The highly doped region of the wafer is substantially etch resistant to an etchant relative to the portion of the wafer being etched.

Abstract: A stress isolating signal path having one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided. The flexible bonding surface may be bonded to external package components or external circuitry using conventional wire bond, epoxy bond, tape automated bonding, flip chip bonding, or the like. The signal path is formed using conventional semiconductor thin film deposition, patterning, and etching techniques. The signal path comprises a conductive material compatible with batch semiconductor manufacturing technology.

Abstract: A circuit for trimming the input offset voltage of an input stage of an op amp includes variable resistors (20, 24) for providing variable voltages in series with the input voltage of the op amp. The voltage drop across the variable resistors is adjusted to compensate for any base-emitter voltage mismatches of the input transistors (12, 14) thereby making the input offset voltage of the op amp equal to zero. Further, the variable resistors can be replaced by resistive networks (40, 42) such that the resistive networks can be adjusted to provide an input stage with a zero temperature coefficient as well as a zero input offset voltage.

Abstract: An improved method of trimming resistors by metal migration by local heating (18,21) of the resistor (23) to allow a reduced level of electric current to be used. The resistor is then trimmed by application of short pulses of high current causing metal migration (22). Each pulse decreases the resistance progressively until a desired final value is achieved. The reduced level of current of the improved method requires a reduced voltage across the resistor thus extending the earlier method to allow higher valued resistors, or lower breakdown voltages. The localized heating (18,21) is also used to anneal the migrated metal after trimming to increase the long term stability of the resistor (23). The intensity of the localized heating (18,21) can be varied to induce a desired shape in the migrated metal (22).

Abstract: A low-cost, quickly prototyped sensor circuit assembly comprises a sensor integrated circuit and an amplifier circuit, wherein all adjustable system resistors are located on the sensor integrated circuit in the form of adjustable thin-film resistive elements whose manufacture requires no new mask layers. An assembly method comprises trimming the sensor and amplifier circuit as a matched pair.

Abstract: A monolithically integrated logic circuit is provided that is programmed by an optical input. A plurality of input/output pads are provided on a semiconductor substrate having a planar surface. A plurality of semiconductor devices and a plurality of light sensitive devices are formed with selected patterns in the surface. At least one metallic layer is formed on the substrate for coupling selected ones of the semiconductor devices, light sensitive devices, and input/output pads for forming a logic circuit, wherein an output of the logic circuit is determined by programming selected ones of the plurality of light sensitive devices by applying light thereto.

Abstract: A bipolar writable array logic device is provided having an output representing a logical AND function and a logical OR function in response to a plurality of input signals. An AND matrix decode and an OR matrix decode are coupled to an input circuit for separately decoding a plurality of input signals. An array of collector sensed memory cells is coupled to the AND matrix decode for selecting desired rows of the collector sensed memory cells. A first plurality of sense amplifiers are coupled between the OR matrix decode and columns of the collector sensed memory cells for providing an ANDed output. Rows of an array of emitter sensed memory cells are coupled to the first plurality of sense amplifiers. A second plurality of sense amplifiers are coupled to columns of the emitter sensed memory cells for providing the bipolar writable array logic device output.