Patents by Inventor IRA LEVENTHAL
IRA LEVENTHAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11940487Abstract: An apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.Type: GrantFiled: January 9, 2023Date of Patent: March 26, 2024Assignee: Advantest Test Solutions, Inc.Inventors: Samer Kabbani, Kazuyuki Yamashita, Ikeda Hiroki, Ira Leventhal, Mohammad Ghazvini, Paul Ferrari, Karthik Ranganathan, Gregory Cruzan, Gilberto Oseguera
-
Publication number: 20240027492Abstract: A test apparatus comprising a tester interface board (TIB) affixed in a slot of a tester rack, wherein the TIB comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT). The test apparatus further comprises a carrier comprising an array of DUTs, wherein the carrier is operable to slide into the slot of the tester rack, and wherein each DUT in the array of DUTs aligns with a respective socket on the TIB. Further, the test apparatus comprises a plurality of socket covers, wherein each socket cover of the plurality of socket covers is operable to actuate a top portion of each DUT of the array of DUTs in the carrier.Type: ApplicationFiled: September 30, 2023Publication date: January 25, 2024Inventors: Karthik Ranganathan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal, Koji Miyauchi, Keith Schaub, Amit Kucheriya, Kotaro Hasegawa, Yoshiyuki Aoki
-
Patent number: 11821913Abstract: A test apparatus comprising a tester interface board (TIB) affixed in a slot of a tester rack, wherein the TIB comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT). The test apparatus further comprises a carrier comprising an array of DUTs, wherein the carrier is operable to slide into the slot of the tester rack, and wherein each DUT in the array of DUTs aligns with a respective socket on the TIB. Further, the test apparatus comprises a plurality of socket covers, wherein each socket cover of the plurality of socket covers is operable to actuate a top portion of each DUT of the array of DUTs in the carrier.Type: GrantFiled: September 30, 2021Date of Patent: November 21, 2023Assignee: Advantest Test Solutions, Inc.Inventors: Karthik Ranganathan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal, Koji Miyauchi, Keith Schaub, Amit Kucheriya, Kotaro Hasegawa, Yoshiyuki Aoki
-
Patent number: 11808812Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: GrantFiled: September 20, 2021Date of Patent: November 7, 2023Assignee: Advantest Test Solutions, Inc.Inventors: Karthik Ranganathan, Gregory Cruzan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal, Hiroki Ikeda, Toshiyuki Kiyokawa
-
Publication number: 20230314512Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: ApplicationFiled: June 6, 2023Publication date: October 5, 2023Inventors: Karthik RANGANATHAN, Gregory CRUZAN, Samer Kabbani, Gilberto Oseguera, Ira Leventhal, Hiroki Ikeda, Toshiyuki Kiyokawa
-
Patent number: 11742055Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: GrantFiled: November 9, 2022Date of Patent: August 29, 2023Assignee: Advantest Test Solutions, Inc.Inventors: Karthik Ranganathan, Gregory Cruzan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal
-
Publication number: 20230228812Abstract: An apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.Type: ApplicationFiled: January 9, 2023Publication date: July 20, 2023Inventors: Samer Kabbani, Kazuyuki Yamashita, Hiroki Ikeda, Ira Leventhal, Mohammad Ghazvini, Paul Ferrari, Karthik Ranganathan, Gregory Cruzan, Gilberto Oseguera
-
Publication number: 20230197185Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: ApplicationFiled: February 19, 2023Publication date: June 22, 2023Inventors: Karthik Ranganathan, Gregory Cruzan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal
-
Publication number: 20230111543Abstract: Embodiments of the present invention provide systems and methods for multidimensional parts average testing for testing devices and analyzing testing results to detect outliers according to embodiments of the present invention. The testing can include calculating multivariate (e.g., bivariate) statistics using delta measurements of like devices, a ratio of measurements, or principal component analysis that identifies eigenvectors and eigenvalues to define meta parameters, for example. Raw test result data can be converted to residual space and robust regression can be performed to prevent outlier results from influencing regression, thereby reducing overkill advantageously.Type: ApplicationFiled: October 8, 2021Publication date: April 13, 2023Inventors: Kenneth Butler, Ira Leventhal, Constantinos Xanthopoulos, Alan Hart, Brian Buras, Keith Schaub
-
Publication number: 20230062440Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: ApplicationFiled: November 9, 2022Publication date: March 2, 2023Inventors: Karthik Ranganathan, Gregory Cruzan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal
-
Patent number: 11587640Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: GrantFiled: November 19, 2021Date of Patent: February 21, 2023Assignee: Advantest Test Solutions, Inc.Inventors: Karthik Ranganathan, Gregory Cruzan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal
-
Patent number: 11549981Abstract: An apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.Type: GrantFiled: September 20, 2021Date of Patent: January 10, 2023Assignee: Advantest Test Solutions, Inc.Inventors: Samer Kabbani, Kazuyuki Yamashita, Hiroki Ikeda, Ira Leventhal, Mohammad Ghazvini, Paul Ferrari, Karthik Ranganathan, Gregory Cruzan, Gilberto Oseguera
-
Publication number: 20220284982Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: ApplicationFiled: November 19, 2021Publication date: September 8, 2022Inventors: Karthik Ranganathan, Gregory Cruzan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal
-
Publication number: 20220137092Abstract: A test apparatus comprising a tester interface board (TIB) affixed in a slot of a tester rack, wherein the TIB comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT). The test apparatus further comprises a carrier comprising an array of DUTs, wherein the carrier is operable to slide into the slot of the tester rack, and wherein each DUT in the array of DUTs aligns with a respective socket on the TIB. Further, the test apparatus comprises a plurality of socket covers, wherein each socket cover of the plurality of socket covers is operable to actuate a top portion of each DUT of the array of DUTs in the carrier.Type: ApplicationFiled: September 30, 2021Publication date: May 5, 2022Inventors: Karthik Ranganathan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal, Koji Miyauchi, Keith Schaub, Amit Kucheriya, Kotaro Hasegawa, Yoshiyuki Aoki
-
Publication number: 20220137129Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.Type: ApplicationFiled: September 20, 2021Publication date: May 5, 2022Inventors: Karthik Ranganathan, Gregory Cruzan, Samer Kabbani, Gilberto Oseguera, Ira Leventhal, Hiroki Ikeda, Toshiyuki Kiyokawa
-
Publication number: 20220107360Abstract: An apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet. cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression a a mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.Type: ApplicationFiled: September 20, 2021Publication date: April 7, 2022Inventors: Samer Kabbani, Kazuyuki Yamashita, Hiroki Ikeda, Ira Leventhal, Mohammad Ghazvini, Paul Ferrari, Karthik Ranganathan, Gregory Cruzan, Gilberto Oseguera
-
Patent number: 11244443Abstract: Provided is an examination apparatus including a target image acquiring section that acquires a target image obtained by capturing an examination target; a target image masking section that masks a portion of the target image; a masked region predicting section that predicts an image of a masked region that is masked in the target image; a reproduced image generating section that generates a reproduced image using a plurality of predicted images predicted respectively for the plurality of masked regions; and a difference detecting section that detects a difference between the target image and the reproduced image.Type: GrantFiled: July 28, 2019Date of Patent: February 8, 2022Assignee: ADVANTEST CORPORATIONInventors: Kosuke Ikeda, Ira Leventhal, Keith Schaub
-
Publication number: 20210027443Abstract: Provided is an examination apparatus including a target image acquiring section that acquires a target image obtained by capturing an examination target; a target image masking section that masks a portion of the target image; a masked region predicting section that predicts an image of a masked region that is masked in the target image; a reproduced image generating section that generates a reproduced image using a plurality of predicted images predicted respectively for the plurality of masked regions; and a difference detecting section that detects a difference between the target image and the reproduced image.Type: ApplicationFiled: July 28, 2019Publication date: January 28, 2021Inventors: Kosuke IKEDA, Ira LEVENTHAL, Keith SCHAUB
-
Patent number: 10701571Abstract: In one embodiment, a test system comprises: a network access point simulation component, a local control component, and a reference component. The network access point simulation component is configured to simulate communication network access point operations comprising test interactions with user equipment. The number of devices under test included in the user equipment and distinct network access points that are coincidentally simulated are variable. The local control component is configured to direct the network access point simulation component and to control the test interactions with the user equipment. The local control component comprises a test executive operable to direct simulation of communication network operations and the test interactions in accordance with information received from the remote control components. The reference component is operable to communicatively couple with the network access point simulation component similar to the user equipment and validate the test interactions.Type: GrantFiled: August 12, 2016Date of Patent: June 30, 2020Assignee: W2BI, INC.Inventors: Dinesh Doshi, Mark Elston, Vipul Jain, Amit Kucheriya, Derek Diperna, Liqun Liu, Ira Leventhal
-
Patent number: 10681570Abstract: In one embodiment, a test system comprises a first interface for communicating with remote devices; a second interface for communicating with local devices; a memory for storing information, including information received from the first interface and second interface; a processor for automatically configuring test system components in accordance with the information stored in the memory. The test system components comprise a network access point simulation component and a local control component. The network access point simulation component is configured to simulate communication network access point operations comprising test interactions with user equipment. The number of devices under test included in the user equipment and distinct network access points that are coincidentally simulated can be variable. The local control component is configured to direct the network access point simulation component and to control the test interactions with the user equipment.Type: GrantFiled: August 12, 2016Date of Patent: June 9, 2020Assignee: W2BI, INC.Inventors: Dinesh Doshi, Mark Elston, Vipul Jain, Derek Diperna, Amit Kucheriya, Liqun Liu, Ira Leventhal