Abstract: Digital logic apparatus for demodulating a received phase-modulated carrier wave wherein phase-shifts between successive signalling intervals encode data elements. A shift register serially stores periodic samples of a squared version of the received wave. Exclusive-OR gates compare pairs of stored wave samples, each pair comprising a sample from a previous signalling interval and a sample from a current signalling interval. At least one of the exclusive-OR gates derives synchronizing signals for a local timing generator. For each data element, an integrator is associated with one of the exclusive-OR gates to accumulate a count related to the time during which pairs of similar samples are sensed by its exclusive-OR gate during each signalling interval. The integrator registering the highest count at the end of a given data interval signifies the data element received during that interval.