Patents by Inventor Iraj Eric Shahvandi

Iraj Eric Shahvandi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6786222
    Abstract: A method for removing particles from a semiconductor processing tool is provided. The method comprises providing a pick-up wafer for picking up particles from a semiconductor processing tool, inserting said pick-up wafer into said semiconductor processing tool and placing the pick-up wafer on a receiving member, applying an electrostatic charge to said pick-up wafer, leaving said pick-up wafer in said semiconductor processing tool for a predetermined dwell time; and removing said pick-up wafer from said semiconductor processing tool. Further, a method for processing semiconductor wafers is provided.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: September 7, 2004
    Assignee: Motorola, Inc.
    Inventors: Larry E. Frisa, Scott S. Kellogg, Grant W. McEwan, Michael N. Montgomery, Iraj Eric Shahvandi
  • Publication number: 20040079385
    Abstract: A method for removing particles from a semiconductor processing tool is provided. The method comprises providing a pick-up wafer for picking up particles from a semiconductor processing tool, inserting said pick-up wafer into said semiconductor processing tool and placing the pick-up wafer on a receiving member, applying an electrostatic charge to said pick-up wafer, leaving said pick-up wafer in said semiconductor processing tool for a predetermined dwell time; and removing said pick-up wafer from said semiconductor processing tool. Further, a method for processing semiconductor wafers is provided.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 29, 2004
    Inventors: Larry E. Frisa, Scott S. Kellogg, Grant W. McEwan, Michael N. Montgomery, Iraj Eric Shahvandi
  • Publication number: 20030203615
    Abstract: A method for reducing the resistance within an opening, such as a via, in a dielectric (230) is described herein. A first barrier layer (250) is formed within the opening and the portion of the first barrier layer (250) at the bottom of the opening is removed, thereby exposing an underlying metal line (210). Deposited within the opening over the first barrier layer (250) and in contact with a conductor (210), a thin second barrier layer (260) forms a barrier between the conductor (210) and subsequently formed conductive material (270 and 280) within the opening. Because the second barrier layer (260) is thin, resistance is minimized between the conductor (210) and the conductive material (270 and 280). Additionally, if the opening is not aligned with the metal line (210), the second barrier layer (260) prevents the conductive material (270 and 280) from degrading an underlying dielectric (220) that may be present underneath the opening.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 30, 2003
    Inventors: Dean J. Denning, Da Zhang, Christopher M. Prindle, Iraj Eric Shahvandi
  • Patent number: 6362098
    Abstract: In a CVD chamber (120) having a chuck (122) to hold a semiconductor substrate (100) and having a plasma generator (121) to generate a plasma (125), a trench in the substrate is filled with dielectric material from ions (126) of the plasma. The ions are forced to move in a direction (127) that is substantially perpendicular to the surface of the substrate by a pulsed unidirectional voltage between the plasma generator and the substrate, by a circular magnetic field, or by a combination of both fields.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: March 26, 2002
    Assignees: Motorola, Inc., Semiconductor 300 GmbH & Co. KG, Infineon Technologies AG
    Inventors: Terry Alan Breeden, Iraj Eric Shahvandi, Michael Thomas Tucker, Olivier Gerard Marc Vatel, Karl Emerson Mautz, Ralf Zedlitz