Abstract: A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.

Abstract: A memory system provides Error Correcting Code (ECC) protection for data stored in a parity enabled memory. The memory may include designated parity locations for data stored in the memory. During write operations, the system may obtain data to write into the memory, compute ECC protection bits for the data, and store the ECC protection bits in locations in the memory designated as parity locations for the data. During read operations, the system may read data from the memory. The system may also read protection bits for the data from locations designated as parity locations for the data. Then, the system may interpret the protection bits as ECC protection bits instead of as parity bits. The system may provide ECC protection for data without additional overhead or memory configuration changes to the parity enabled memory.

Abstract: A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.