Abstract: A high frequency switch circuit according to the present invention includes a control-voltage-generating circuit. The control-voltage-generating circuit includes a depletion type field-effect transistor, an external-control-signal-input terminal, an internal-control-voltage-output terminal, and a power-receiving terminal of the control-voltage-generating circuit. The field-effect transistor has a grounded gate, a source connected to the external-control-signal-input terminal, and a drain connected to the power-receiving terminal. The internal-control-voltage-output terminal is connected to an electrical connection path between the drain of the field-effect transistor and the power-receiving terminal.

Abstract: This invention provides a receiver in which the calibration time by repeated operations to correct phase mismatch and amplitude mismatch between I and Q signals can be reduced. The receiver comprises mixers which convert received RF signals into quadrature modulated IF signals, signal paths which filter and amplify and output the quadrature modulated signals output from the mixers, a calibration circuit which calibrates phase and amplitude mismatches between the I and Q components of the quadrature modulated signals output through the signal paths, a frequency converter which, when the mixers or the signal paths selected output calibration signals with IF frequency instead of the quadrature modulated signals, converts the calibration signals into those with a frequency higher than IF frequency, and an arithmetic operation circuit which calculates phase and amplitude mismatches from the calibration signals output by the frequency converter and outputs calculation results.

Abstract: A 90-degree phase delay power divider part PSPD is connected to an input side of a carrier amplifier Amp1 and a peak amplifier Amp2, and a variable electric length power combiner VTL2 is connected to an output side thereof. A control signal Sig is applied through a control terminal Ctrl of the variable electric length power combiner VTL2, and adjustment is performed in correspondence to a carrier frequency band of a carrier signal RFs so that an electric length of the variable electric length power combiner VTL2 becomes nearly 90 degrees. As a result, an electric length of an output power combining circuit of a Doherty type amplifier can be made variable, and a power-added efficiency can be enhanced for a multi-band or broad band.

Abstract: A 90-degree phase delay power divider part PSPD is connected to an input side of a carrier amplifier Amp1 and a peak amplifier Amp2, and a variable electric length power combiner VTL2 is connected to an output side thereof. A control signal Sig is applied through a control terminal Ctrl of the variable electric length power combiner VTL2, and adjustment is performed in correspondence to a carrier frequency band of a carrier signal RFs so that an electric length of the variable electric length power combiner VTL2 becomes nearly 90 degrees. As a result, an electric length of an output power combining circuit of a Doherty type amplifier can be made variable, and a power-added efficiency can be enhanced for a multi-band or broad band.

Abstract: A multi-band radio module for selectively supplying received signals in a plurality of frequency bands to a low noise amplifier via an input impedance matching circuit by switching over the operation mode of the low noise amplifier is comprised of: a pre-stage amplification unit including a plurality of fundamental amplifiers connected to one another in parallel, the fundamental amplifiers sharing a load impedance connected to a source voltage and a grounded degeneration impedance and having input signal lines commonly connected to an input impedance matching circuit; a post-stage amplifier to which the output signals of the plurality of fundamental amplifiers are commonly inputted; and a bias control unit for selectively turning on the fundamental amplifiers, wherein the input impedance of the low noise amplifier is selectively optimized for the matching circuit depending on the RF band to be received.

Abstract: This invention provides a receiver in which the calibration time by repeated operations to correct phase mismatch and amplitude mismatch between I and Q signals can be reduced. The receiver comprises mixers which convert received RF signals into quadrature modulated IF signals, signal paths which filter and amplify and output the quadrature modulated signals output from the mixers, a calibration circuit which calibrates phase and amplitude mismatches between the I and Q components of the quadrature modulated signals output through the signal paths, a frequency converter which, when the mixers or the signal paths selected output calibration signals with IF frequency instead of the quadrature modulated signals, converts the calibration signals into those with a frequency higher than IF frequency, and an arithmetic operation circuit which calculates phase and amplitude mismatches from the calibration signals output by the frequency converter and outputs calculation results.

Abstract: In order to rapidly control the gains of a plurality of variable gain amplifiers VGAs, each of gain control circuits is configured to determine a gain to be set therein, based on gain control information received from other gain control circuits existing in its preceding stage or stages and the signal level detected by a level detector circuit connected thereto. By carrying out such gain control, a total application gain is stabilized more quickly by gain control. Therefore, even in receiving systems that the preparation period for reception is very short, desired gain control is achieved within this period and stable data reception can be performed.

Abstract: In order to rapidly control the gains of a plurality of variable gain amplifiers VGAs, each of gain control circuits is configured to determine a gain to be set therein, based on gain control information received from other gain control circuits existing in its preceding stage or stages and the signal level detected by a level detector circuit connected thereto. By carrying out such gain control, a total application gain is stabilized more quickly by gain control. Therefore, even in receiving systems that the preparation period for reception is very short, desired gain control is achieved within this period and stable data reception can be performed.