Patents by Inventor Irene Junjuan Xu
Irene Junjuan Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9535861Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.Type: GrantFiled: February 17, 2016Date of Patent: January 3, 2017Assignee: Micron Technology, Inc.Inventors: David R. Brown, Harold B Noyes, Irene Junjuan Xu, Paul Glendenning
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Patent number: 9509312Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.Type: GrantFiled: August 21, 2015Date of Patent: November 29, 2016Assignee: Micron Technology, Inc.Inventors: Harold B Noyes, David R. Brown, Paul Glendenning, Irene Junjuan Xu
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Publication number: 20160239440Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.Type: ApplicationFiled: February 17, 2016Publication date: August 18, 2016Inventors: David R. Brown, Harold B Noyes, Irene Junjuan Xu, Paul Glendenning
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Patent number: 9275290Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.Type: GrantFiled: March 24, 2014Date of Patent: March 1, 2016Assignee: Micron Technology, Inc.Inventors: David R. Brown, Harold B Noyes, Irene Junjuan Xu, Paul Glendenning
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Publication number: 20150365091Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.Type: ApplicationFiled: August 21, 2015Publication date: December 17, 2015Inventors: Harold B. Noyes, David R. Brown, Paul Glendenning, Irene Junjuan Xu
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Patent number: 9118327Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.Type: GrantFiled: November 22, 2013Date of Patent: August 25, 2015Assignee: Micron Technology, Inc.Inventors: Harold B Noyes, David R. Brown, Paul Glendenning, Irene Junjuan Xu
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Publication number: 20140204956Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.Type: ApplicationFiled: March 24, 2014Publication date: July 24, 2014Applicant: Micron Technology, Inc.Inventors: David R. Brown, Harold B. Noyes, Irene Junjuan Xu, Paul Glendenning
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Patent number: 8680888Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.Type: GrantFiled: December 15, 2011Date of Patent: March 25, 2014Assignee: Micron Technologies, Inc.Inventors: David R. Brown, Harold B Noyes, Irene Junjuan Xu, Paul Glendenning
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Publication number: 20140077838Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.Type: ApplicationFiled: November 22, 2013Publication date: March 20, 2014Inventors: Harold B. Noyes, David R. Brown, Paul Glendenning, Irene Junjuan Xu
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Patent number: 8593175Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.Type: GrantFiled: December 15, 2011Date of Patent: November 26, 2013Assignee: Micron Technology, Inc.Inventors: Harold B Noyes, David R. Brown, Paul Glendenning, Irene Junjuan Xu
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Publication number: 20130156043Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Applicant: Micron Technology, Inc.Inventors: David R. Brown, Harold B Noyes, Irene Junjuan Xu, Paul Glendenning