Patents by Inventor Irene Sperl

Irene Sperl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming a silicon dioxide layer
    Patent number: 7081384
    Abstract: The present invention refers to a method of forming a silicon dioxide layer by thermally oxidizing at least one monocrystalline silicon surface region on a semiconductor substrate. The silicon surface region has a curved surface. The method can include providing a semiconductor substrate having at least one monocrystalline silicon surface region having a curved surface, roughening the surface of the at least one monocrystalline silicon surface region to produce a layer of porous silicon, and thermally oxidizing the at least one roughened monocrystalline silicon surface.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: July 25, 2006
    Assignee: Infineon Technologies, AG
    Inventors: Albert Birner, Matthias Goldbach, Irene Sperl
  • Method of forming a silicon dioxide layer
    Publication number: 20040219758
    Abstract: The present invention refers to a method of forming a silicon dioxide layer by thermally oxidizing at least one monocrystalline silicon surface region on a semiconductor substrate. The silicon surface region has a curved surface. The method can include providing a semiconductor substrate having at least one monocrystalline silicon surface region having a curved surface, roughening the surface of the at least one monocrystalline silicon surface region to produce a layer of porous silicon, and thermally oxidizing the at least one roughened monocrystalline silicon surface.
    Type: Application
    Filed: April 14, 2004
    Publication date: November 4, 2004
    Inventors: Albert Birner, Matthias Goldbach, Irene Sperl
  • Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive regions
    Patent number: 6716678
    Abstract: A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: April 6, 2004
    Assignee: Infineon Technologies AG
    Inventors: Matthias Lehr, Uwe Schilling, Veronika Polei, Irene Sperl
  • Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive regions
    Publication number: 20030157752
    Abstract: A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.
    Type: Application
    Filed: March 3, 2003
    Publication date: August 21, 2003
    Inventors: Matthias Lehr, Uwe Schilling, Veronika Polei, Irene Sperl
  • Method for increasing the trench capacitance
    Patent number: 6544856
    Abstract: A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a wet-chemical etching is additionally performed. An n+-doped substrate results from the driving-out of the arsenic glass being widened in the trench, by about 20 nm, selectively both with respect to the lightly doped substrate and with respect to the oxide layer and with respect to the nitride layer.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: April 8, 2003
    Assignee: Infineon Technologies AG
    Inventors: Klaus-Dieter Morhard, Irene Sperl, Klaus Penner
  • Method for increasing the trench capacitance
    Publication number: 20020018377
    Abstract: A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a wet-chemical etching is additionally performed. An n+-doped substrate results from the driving-out of the arsenic glass being widened in the trench, by about 20 nm, selectively both with respect to the lightly doped substrate and with respect to the oxide layer and with respect to the nitride layer.
    Type: Application
    Filed: June 13, 2001
    Publication date: February 14, 2002
    Inventors: Klaus-Dieter Morhard, Irene Sperl, Klaus Penner