Patents by Inventor Irene Y. L. Lin

Irene Y. L. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit design having aligned power staples
    Patent number: 10242946
    Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Irene Y. L. Lin, Lei Yuan, Mahbub Rashed
  • CIRCUIT DESIGN HAVING ALIGNED POWER STAPLES
    Publication number: 20180218981
    Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.
    Type: Application
    Filed: January 27, 2017
    Publication date: August 2, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Irene Y. L. Lin, Lei Yuan, Mahbub Rashed