Patents by Inventor Irene Y. Lin
Irene Y. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367360Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.Type: ApplicationFiled: August 2, 2022Publication date: November 17, 2022Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 11444031Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.Type: GrantFiled: September 30, 2020Date of Patent: September 13, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20210013150Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 10833018Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.Type: GrantFiled: July 3, 2019Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20190326219Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20160268204Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.Type: ApplicationFiled: May 25, 2016Publication date: September 15, 2016Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 9355910Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.Type: GrantFiled: December 13, 2011Date of Patent: May 31, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8598633Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.Type: GrantFiled: January 16, 2012Date of Patent: December 3, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8581348Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.Type: GrantFiled: December 13, 2011Date of Patent: November 12, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Mahbub Rashed, Steven Soss, Jongwook Kye, Irene Y. Lin, James Benjamin Gullette, Chinh Nguyen, Jeff Kim, Marc Tarabbia, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20130181289Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.Type: ApplicationFiled: January 16, 2012Publication date: July 18, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20130146982Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Mahbub Rashed, Steven Soss, Jongwook Kye, Irene Y. Lin, James Benjamin Gullette, Chinh Nguyen, Jeff Kim, Marc Tarabbia, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20130146986Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan