Abstract: A selective call radio (300) includes a memory (100), which in turn includes one or more memory elements; a row and column decoder (110, 112) coupled to the one or more memory elements, an address and data bus (102, 108). A first portion of the address bus is coupled to the row decoder, and a second portion of the address bus is coupled to the column decoder. The data bus is coupled to the column decoder. Each of the one or more memory elements has a memory map (FIG. 3) determined by: mapping each memory element to multiple addresses of the memory's memory space and, for each address mapped to a memory element, mapping the memory element to a corresponding bit range of the data bus.

Abstract: A controller circuit (100) includes an aliasing circuit (261) for efficiently transferring a set of peripheral data words between a microprocessor (130) and a serial peripheral device (140) that has a first in and first out (FIFO) register (220). The aliasing circuit aliases sequential addresses within a predetermined range of addresses that are generated by the microprocessor during a load multiple or store multiple command, wherein each of the sequential addresses is associated with one peripheral data word of the set of peripheral data words. The serial peripheral device comprises the FIFO register and a data bus register (210) for transferring each peripheral data word between the FIFO register and the microprocessor. A central processing unit (CPU) (125) of the microprocessor uses a CPU word that is not necessarily the same length as the peripheral data word.