Abstract: This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.

Abstract: A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.

Abstract: A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.

Abstract: This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.