Patents by Inventor Irina Yuryevna Bashkirova

Irina Yuryevna Bashkirova has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Area-efficient ESD protection inside standard cells
    Patent number: 11862625
    Abstract: An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 2, 2024
    Assignee: NXP USA, Inc.
    Inventors: Michael A. Stockinger, Mohamed Suleman Moosa, Vasily Vladimirovich Korolev, Irina Yuryevna Bashkirova, Olga Olegovna Sibagatullina
  • AREA-EFFICIENT ESD PROTECTION INSIDE STANDARD CELLS
    Publication number: 20230223394
    Abstract: An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 13, 2023
    Inventors: Michael A. Stockinger, Mohamed Suleman Moosa, Vasily Vladimirovich Korolev, Irina Yuryevna Bashkirova, Olga Olegovna Sibagatullina