Patents by Inventor Iris Lu
Iris Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929125Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.Type: GrantFiled: June 23, 2021Date of Patent: March 12, 2024Assignee: SanDisk Technologies LLCInventors: Tai-Yuan Tseng, Chia-Kai Chou, Iris Lu
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Patent number: 11915769Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.Type: GrantFiled: May 16, 2022Date of Patent: February 27, 2024Assignee: SanDisk Technologies LLCInventors: Kei Kitamura, Iris Lu, Tai-Yuan Tseng
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Patent number: 11901018Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.Type: GrantFiled: December 27, 2021Date of Patent: February 13, 2024Assignee: SanDisk Technologies LLCInventors: Iris Lu, Tai-Yuan Tseng, Chia-Kai Chou
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Publication number: 20230368852Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.Type: ApplicationFiled: May 16, 2022Publication date: November 16, 2023Applicant: SanDisk Technologies LLCInventors: Kei Kitamura, Iris Lu, Tai-Yuan Tseng
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Patent number: 11798631Abstract: Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.Type: GrantFiled: October 21, 2021Date of Patent: October 24, 2023Assignee: SanDisk Technologies LLCInventors: Iris Lu, Tai-Yuan Tseng
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Patent number: 11699502Abstract: Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.Type: GrantFiled: December 14, 2021Date of Patent: July 11, 2023Assignee: SanDisk Technologies LLCInventors: Iris Lu, Yan Li, Ohwon Kwon
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Publication number: 20230207022Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: SanDisk Technologies LLCInventors: Iris Lu, Tai-Yuan Tseng, Chia-Kai Chou
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Publication number: 20230187014Abstract: Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: SanDisk Technologies LLCInventors: Iris Lu, Yan Li, Ohwon Kwon
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Publication number: 20230130365Abstract: Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.Type: ApplicationFiled: October 21, 2021Publication date: April 27, 2023Applicant: SanDisk Technologies LLCInventors: Iris Lu, Tai-Yuan Tseng
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Publication number: 20220415415Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Applicant: SanDisk Technologies LLCInventors: Tai-Yuan Tseng, Chia-Kai Chou, Iris Lu
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Patent number: 10967023Abstract: Disclosed is a Chinese medicinal composition prepared from the following medical raw materials in parts by weight: 1 part of ginseng, 0.8-1.5 parts of ginkgo leaf and 0.018-0.030 part of stigma croci.Type: GrantFiled: July 9, 2019Date of Patent: April 6, 2021Assignee: Shineway Pharmaceutical Group Ltd.Inventors: Jianxun Liu, Vivian Zhang, Zhigang Li, Shyflysky Zhang, Xiuwei Guan, Iris Lu, Weibo Gao, Li Xu, Wenting Song
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Publication number: 20190328810Abstract: Disclosed are a Chinese medicinal composition for preventing or treating cardiovascular and cerebrovascular diseases and/or dementia, and a preparation method and use thereof. The composition is prepared from the following medical raw materials in parts by weight: 1 part of ginseng, 0.8-1.5 parts of ginkgo leaf and 0.018-0.030 part of stigma croci.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Jianxun Liu, Vivian Zhang, Zhigang Li, Shyflysky Zhang, Xiuwei Guan, Iris Lu, Weibo Gao, Li Xu, Wenting Song
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Publication number: 20170354700Abstract: Disclosed are a Chinese medicinal composition for preventing or treating cardiovascular and cerebrovascular diseases and/or dementia, and a preparation method and use thereof. The composition is prepared from the following medical raw materials in parts by weight: 1 part of ginseng, 0.8-1.5 parts of ginkgo leaf and 0.018-0.030 part of stigma croci.Type: ApplicationFiled: December 29, 2015Publication date: December 14, 2017Inventors: Jianxun Liu, Vivian Zhang, Zhigang Li, Shyflysky Zhang, Xiuwei Guan, Iris Lu, Weibo Gao, Li Xu, Wenting Song