Patents by Inventor Irving G. Baysah
Irving G. Baysah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10649511Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: GrantFiled: April 29, 2019Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Irving G Baysah, John S Dodson, Karthick Rajamani, Eric E Retter, Scot H Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S Allen-Ware
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Patent number: 10614004Abstract: Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes allocating, by a memory controller, a reserved portion of the memory controller to execute transactions. The method further includes receiving, by the memory controller, a priority based transaction from a processor to the memory. The method further includes determining, by the memory controller, whether to accommodate the priority based transaction based at least in part on a current processing state of the memory controller. The method further includes, based at least in part on determining to accommodate the priority based transaction, accommodating the priority based transaction by performing at least one of dropping a speculative command in a queue or using the reserved portion of the memory controller to execute the priority based transaction.Type: GrantFiled: July 23, 2018Date of Patent: April 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Irving G. Baysah, Prasanna Jayaraman
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Publication number: 20190250682Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S. Allen-Ware
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Patent number: 10317964Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: GrantFiled: January 5, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Irving G Baysah, John S Dodson, Karthick Rajamani, Eric E Retter, Scot H Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S Allen-Ware
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Patent number: 10268615Abstract: A Local Timer Engine (LTE) is disclosed. For an initiator in a computing system, the LTE measures a respective time delay for each of a plurality of routes between the initiator and a plurality of destinations. For each of the plurality of routes, the LTE determines a respective timeout value based on the measured respective time delay for the route and determines a unique memory mapped address identifying the route. The initiator sends a request to the LTE for a timeout value. The LTE determines a proper timeout value and provides the proper timeout value to the initiator.Type: GrantFiled: August 22, 2017Date of Patent: April 23, 2019Assignee: International Business Machines CorporationInventors: Irving G. Baysah, Edgar R. Cordero, Marc A. Gollub, Lucus W. Mulkey, Anuwat Saetow
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Publication number: 20190065421Abstract: A Local Timer Engine (LTE) is disclosed. For an initiator in a computing system, the LTE measures a respective time delay for each of a plurality of routes between the initiator and a plurality of destinations. For each of the plurality of routes, the LTE determines a respective timeout value based on the measured respective time delay for the route and determines a unique memory mapped address identifying the route. The initiator sends a request to the LTE for a timeout value. The LTE determines a proper timeout value and provides the proper timeout value to the initiator.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: Irving G. BAYSAH, Edgar R. CORDERO, Marc A. GOLLUB, Lucus W. MULKEY, Anuwat SAETOW
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Publication number: 20180329628Abstract: Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes allocating, by a memory controller, a reserved portion of the memory controller to execute transactions. The method further includes receiving, by the memory controller, a priority based transaction from a processor to the memory. The method further includes determining, by the memory controller, whether to accommodate the priority based transaction based at least in part on a current processing state of the memory controller. The method further includes, based at least in part on determining to accommodate the priority based transaction, accommodating the priority based transaction by performing at least one of dropping a speculative command in a queue or using the reserved portion of the memory controller to execute the priority based transaction.Type: ApplicationFiled: July 23, 2018Publication date: November 15, 2018Inventors: Irving G. Baysah, Prasanna Jayaraman
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Patent number: 10073629Abstract: Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: The method may further include: allocating, by a memory controller, a reserved portion of the memory controller to process prioritized transactions; receiving, by the memory controller, a request transaction from a processor to the memory, wherein the request transaction comprises a priority; determining, by the memory controller, whether the priority of the request transaction is above a priority threshold; and responsive to determining that the priority of the request transaction is above the priority threshold, executing the request using the reserved portion of the memory controller.Type: GrantFiled: December 13, 2016Date of Patent: September 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Irving G. Baysah, Prasanna Jayaraman
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Publication number: 20180165008Abstract: Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: The method may further include: allocating, by a memory controller, a reserved portion of the memory controller to process prioritized transactions; receiving, by the memory controller, a request transaction from a processor to the memory, wherein the request transaction comprises a priority; determining, by the memory controller, whether the priority of the request transaction is above a priority threshold; and responsive to determining that the priority of the request transaction is above the priority threshold, executing the request using the reserved portion of the memory controller.Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Inventors: Irving G. Baysah, Prasanna Jayaraman
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Publication number: 20160132085Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: ApplicationFiled: January 5, 2016Publication date: May 12, 2016Inventors: Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S. Allen-Ware
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Patent number: 9318171Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.Type: GrantFiled: September 30, 2014Date of Patent: April 19, 2016Assignee: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
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Patent number: 9142272Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.Type: GrantFiled: March 15, 2013Date of Patent: September 22, 2015Assignee: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
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Patent number: 9136987Abstract: Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted.Type: GrantFiled: March 15, 2013Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Mark R. Hodges, Irving G. Baysah, John S. Dodson, Patrick J. Meaney, Glenn D. Gilda
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Publication number: 20150019831Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
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Publication number: 20140281326Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
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Publication number: 20140281783Abstract: Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Mark R. Hodges, Irving G. Baysah, John S. Dodson, Patrick J. Meaney, Glenn D. Gilda
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System to improve miscorrection rates in error control code through buffering and associated methods
Patent number: 8176391Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.Type: GrantFiled: January 31, 2008Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Irving G. Baysah, Timothy J. Dell, Luis A. Lastras-Montano, Warren E. Maule, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright -
System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods
Publication number: 20100299576Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.Type: ApplicationFiled: January 31, 2008Publication date: November 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Irving G. Baysah, Timothy J. Dell, Luis A. Lastras-Montano, Warren E. Maule, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright