Abstract: A semiconductor package includes a substrate and a semiconductor chip which includes an active surface with a plurality of chip contact areas. The chip is electrically connected to the substrate. The substrate includes a sheet of core material, a plurality of upper conducting traces and upper contact pads on its upper surface, a second plurality of lower conductive traces and external contact areas on its bottom surface. A plurality of conducting vias connect the conducting traces and lower conducting traces. The substrate also includes a plurality of vent holes and a layer of solder resist covering the upper and lower surfaces of the substrate leaving the contact areas free from solder resist.