Patents by Inventor Irwin D. Rathbun

Irwin D. Rathbun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7642181
    Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: January 5, 2010
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Irwin D. Rathbun, Bryan D. Sendelweck, Thomas S. Moss, III
  • Publication number: 20080290426
    Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.
    Type: Application
    Filed: August 4, 2008
    Publication date: November 27, 2008
    Applicant: Atmel Corporation
    Inventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek
  • Patent number: 7407851
    Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: August 5, 2008
    Inventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek